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m68hc08 microcontrollers freescale.com mc68hc908as32a data sheet mc68hc908as32a rev. 2.0 05/2006

mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2005, 2006. all rights reserved. mc68hc908as32a data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/
revision history mc68hc908as32a data sheet, rev. 2.0 4 freescale semiconductor the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) september, 2005 1.0 reformatted to meet new publications guidelines. modules updated with additional data throughout 1.4.16 bdlc receive pin (bdrxd) ? corrected name of bdlc receive pin to bdrxd. 25 removed keyboard interface module n/a removed timer interface module b removed all references to timb and tbclk n/a may, 2006 2.0 figure 1-3. 64-pin qfp assignments (top view) ? added pin assignment diagram for the 64-pin qfp. 23 figure 2-2. i/o data, status and control registers ? corrected two register entries: spi status and control register (spscr) flash control register (flcr) 32 38 chapter 20 ordering information and mechanical specifications ? added information pertaining to the 64-pin quad flag pack (qfp). 271
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 chapter 3 analog-to-digital co nverter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 4 byte data link cont roller (bdlc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 5 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 chapter 6 configuration regist er (config1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 chapter 7 configuration regist er (config2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 8 computer operating properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 chapter 9 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 chapter 10 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 chapter 11 low-voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 chapter 12 programmable interr upt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 chapter 13 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 chapter 14 serial communications interf ace (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 chapter 15 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 chapter 16 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 chapter 17 timer interface modul e (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 chapter 18 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 chapter 19 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 chapter 20 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . 271
list of chapters mc68hc908as32a data sheet, rev. 2.0 6 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.1 power supply pins (v dd and v ss ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.3 external reset pin (rst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.5 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.6 analog power supply pin (v dda/ v ddaref ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.7 analog ground pin (v ssa /v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.8 adc reference high voltage pin (v refh ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.9 port a input/output (i/o) pins (pta7?pta0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.10 port b i/o pins (ptb7/atd7?ptb0/atd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.11 port c i/o pins (ptc4?ptc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.12 port d i/o pins (ptd6?ptd0/atd8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.13 port e i/o pins (pte7/spsck?pte0/txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.14 port f i/o pins (ptf3?ptf0/tch2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.15 bdlc transmit pin (bdtxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.16 bdlc receive pin (bdrxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 input/output (i/o) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5 additional status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6 vector addresses and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.7 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 electrically erasable pr ogrammable read-only memory (eeprom) . . . . . . . . . . . . . . . . . . . . 40 2.8.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8.1.1 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.1.2 eeprom timebase requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.1.3 eeprom program/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.1.4 eeprom block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.8.1.5 eeprom programming and erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8.1.6 program/erase using auto bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
table of contents mc68hc908as32a data sheet, rev. 2.0 8 freescale semiconductor 2.8.1.7 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.8.1.8 eeprom erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.8.2 eeprom register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.8.2.1 eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 2.8.2.2 eeprom array configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.8.2.3 eeprom nonvolatile register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.8.2.4 eeprom timebase divider register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.8.2.5 eeprom timebase divider nonvolat ile register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.8.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.8.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.8.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.9 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.9.1 flash control and block protect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.9.1.1 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.9.1.2 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.9.2 flash block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.9.3 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.9.4 flash mass erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.9.5 flash program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.9.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.9.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.9.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 chapter 3 analog-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6.1 adc analog power pin (v ddaref )/adc voltage reference pin (v refh ) . . . . . . . . . . . . . . 62 3.6.2 adc analog ground pin (v ssa )/adc voltage reference low pin (v refl ) . . . . . . . . . . . . 63 3.6.3 adc voltage in (adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.7.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.7.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
table of contents mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 9 chapter 4 byte data link c ontroller (bdlc) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3.1 bdlc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.1.1 power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1.2 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1.3 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1.4 bdlc wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1.5 bdlc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1.6 digital loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.1.7 analog loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.4 bdlc mux interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.4.1 rx digital filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4.1.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4.1.2 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4.2 j1850 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.3 j1850 vpw symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.4 j1850 vpw valid/invalid bits and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.4.5 message arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5 bdlc protocol handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.1 protocol architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.2 rx and tx shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.3 rx and tx shadow registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.4 digital loopback multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.5 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.5.1 4x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.5.2 receiving a message in block mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.5.3 transmitting a message in block mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.5.4 j1850 bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.5.5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.6 bdlc cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.6.1 bdlc analog and roundtrip delay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.6.2 bdlc control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.6.3 bdlc control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.6.4 bdlc state vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.6.5 bdlc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
table of contents mc68hc908as32a data sheet, rev. 2.0 10 freescale semiconductor chapter 5 clock generator module (cgm) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.1 crystal oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.2.1 circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.2.2 acquisition and tracking modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.2.3 manual and automatic pll bandwidth modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.2.4 programming the pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.2.5 special programming exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3.3 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.3.4 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 5.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 5.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.4 analog power pin (v dda ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.6 crystal output frequency signal (cgmxclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.5 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.5.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.5.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.5.3 pll programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 08 5.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.8 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.9 acquisition/lock time specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.9.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 5.9.2 parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.9.3 choosing a filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.9.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 chapter 6 configuration regi ster (config1) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 chapter 7 configuration regi ster (config2) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
table of contents mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 11 chapter 8 computer operatin g properly (cop) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3.6 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.3.7 copd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.3.8 copl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.8 cop module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 chapter 9 central processor unit (cpu) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 chapter 10 external interrupt module (irq) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
table of contents mc68hc908as32a data sheet, rev. 2.0 12 freescale semiconductor chapter 11 low-voltage inhibit (lvi) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.3.3 false reset protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 chapter 12 programmable interrupt timer (pit) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.4 pit counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.6 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.7.1 pit status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 47 12.7.2 pit counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.7.3 pit counter modulo registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 49 chapter 13 input/output ports 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.5.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
table of contents mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 13 13.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.6.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.7 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.7.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13.7.2 data direction register f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 chapter 14 serial communications interface (sci) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 0 14.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.6 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.7.1 pte0/sctxd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 14.7.2 pte1/scrxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 14.8.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 14.8.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.8.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.8.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.8.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 14.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 14.8.7 sci baud rate register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
table of contents mc68hc908as32a data sheet, rev. 2.0 14 freescale semiconductor chapter 15 system integrati on module (sim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.3.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 95 15.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 15.5 program exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 15.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.7.1 sim break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 chapter 16 serial peripheral interface (spi) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.3 pin name and register name conventi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.4.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.5 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.5.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 16.5.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.5.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.5.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
table of contents mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 15 16.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.6.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.6.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.8 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.9 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.10 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.11 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.12 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 16.12.1 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 16.12.2 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 16.12.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.12.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.12.5 v ss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 16.13 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 16.13.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 16.13.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.13.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 chapter 17 timer interface module (tim) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.3.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 17.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 31 17.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 17.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.6 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.7.1 tim clock pin (ptd6/atd14/tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.7.2 tim channel i/o pins (ptf3/tch5?ptf0/tch2 and pte3/tch1?pte2/tch0) . . . . . . 236 17.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.8.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 36 17.8.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
table of contents mc68hc908as32a data sheet, rev. 2.0 16 freescale semiconductor 17.8.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 17.8.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.8.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 chapter 18 development support 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 18.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 18.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 18.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 18.2.1.2 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 18.2.1.3 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 47 18.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 18.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 18.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 18.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 18.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 18.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 18.3.1.1 monitor mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3.1.2 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3.1.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18.3.1.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18.3.1.5 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18.3.1.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 chapter 19 electrical specifications 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.5 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.6 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 19.7 analog-to-digital converter (adc) char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 19.8 5.0 vdc 0.5 v serial peripheral interface (spi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 19.9 clock generator module (cgm) characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.9.1 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.9.2 cgm component information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.9.3 cgm acquisition/lock time information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 19.10 timer module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 19.11 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 19.11.1 ram memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 67 19.11.2 eeprom memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 19.11.3 flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8
table of contents mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 17 19.12 byte data link controller (bdlc) c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 19.12.1 bdlc transmitter vpw symbol timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 19.12.2 bdlc receiver vpw symbol timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 19.12.3 bdlc transmitter dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 19.12.4 bdlc receiver dc electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 chapter 20 ordering information and m echanical specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 20.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 20.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
table of contents mc68hc908as32a data sheet, rev. 2.0 18 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 19 chapter 1 general description 1.1 introduction the mc68hc908as32a is a member of the low-co st, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. 1.2 features features include: ? high-performance m68hc08 architecture fully upward-compatible object code wi th m6805, m146805, and m68hc05 families 8.4 mhz internal bus frequency 32,256 bytes of flash electrically erasable read-only memory (flash) flash data security (1) 512 bytes of on-chip electrically erasable pr ogrammable read-only memory with security option (eeprom) (1) 1 kbyte of on-chip ram clock generator module (cgm) serial peripheral interface module (spi) serial communications interface module (sci) 8-bit, 15-channel analog-to-digital converter (adc) 16-bit, 6-channel timer interface module (tim) programmable interrupt timer (pit) system protection features ? computer operating properly (cop) with optional reset ? low-voltage detection with optional reset ? illegal opcode detection with optional reset ? illegal address detection with optional reset low-power design (fully static with stop and wait modes) master reset pin and power-on reset sae j1850 byte data link controller digital module 1. no security feature is absolutely secu re. however, freescale?s strategy is to make reading or copying the flash and eeprom difficult for unauthorized users.
general description mc68hc908as32a data sheet, rev. 2.0 20 freescale semiconductor features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications c language support 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908as32a.
mcu block diagram mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 21 figure 1-1. mcu block diagram for the mc68hc908as32a break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
general description mc68hc908as32a data sheet, rev. 2.0 22 freescale semiconductor 1.4 pin assignments the mc68hc908as32a is available in a 52-pin plastic leaded chip carrier (plcc) and a 64-pin quad flat pack (qfp). figure 1-2 and figure 1-3 show the pin assignments for these packages. figure 1-2. 52-pin plcc assignments (top view) 46 34 bdrxd cgmxfc ptb4/atd4 ptf3/tch5 ptf2/tch4 ptf1/tch3 ptf0/tch2 rst irq ptc4 bdtxd pte0/txd pte1/rxd pte2/tch0 pte3/tch1 ptd3/atd11 ptd2/atd10 ptd1/atd9 ptd0/atd8 ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa /v refl v dda /v ddaref v refh ptd6/atd14/tclk ptd5/atd13 ptd4/atd12 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte5/miso pte4/ss pte6/mosi pte7/spsck v ss v dd pta0 pta1 pta2 pta3 pta4 pta5 pta6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 45 44 43 42 41 40 39 38 37 36 35 7 6 5 4 3 2 1 52 51 50 49 48 47
pin assignments mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 23 figure 1-3. 64-pin qfp assignments (top view) note the following pin descriptions are just a quick reference. for a more detailed representation, see chapter 13 input/output ports . 1.4.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to prov ide power supply bypassing at the mcu as shown in figure 1-4 . place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency response ceramic capacitor for c1. c2 is an optional bu lk current bypass capacitor for use in applications that require the port pins to source high current levels. nc cgmxfc ptb7/atd7 ptf3/tch5 ptf2/tch4 ptf1/tach3 ptf0/tach2 rst irq ptc4 bdrxd bdtxd nc pte0/txd pte1/rxd pte2/tach0 pte3/tach1 nc ptd3/atd11 ptd2/atd10 nc nc ptd1/atd9 ptd0/atd8 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa v dda v refh nc ptd6/atd14/tclk ptd5 /atd13 ptd4/ atd12 nc nc ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ss pte5/miso pte7/spsck v ss v dd nc nc nc pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 nc 48 49
general description mc68hc908as32a data sheet, rev. 2.0 24 freescale semiconductor figure 1-4. power supply bypassing v ss is also the ground for the port output buffers and the ground return for the serial clock in the spi. see chapter 16 serial peripheral interface (spi) for more information. note v ss must be grounded for proper mcu operation. 1.4.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. see chapter 5 clock generator module (cgm) for more information. 1.4.3 external reset pin (rst ) a 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. see chapter 15 system integration module (sim) for more information. 1.4.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. see chapter 10 external interrupt module (irq) for more information. 1.4.5 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacitor conne ction for the clock generator module (cgm). see chapter 5 clock generator module (cgm) for more information. 1.4.6 analog power supply pin (v dda/ v ddaref ) v dda/ v ddaref is the power supply pin for the analog portion of the adc and the cgm. see chapter 3 analog-to-digital converter (adc) and chapter 5 clock generator module (cgm) for more information. mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown r epresent typical applications.
pin assignments mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 25 1.4.7 analog ground pin (v ssa /v refl ) the v ssa /v refl pin provides both the analog ground connection and the reference low voltage for the adc as well as the ground connection for the cgm. see chapter 3 analog-to-digital converter (adc) and chapter 5 clock generator module (cgm) for more information. 1.4.8 adc reference high voltage pin (v refh ) v refh provides the reference high voltage for the adc. see chapter 3 analog-to-digital converter (adc) for more information. 1.4.9 port a input/out put (i/o) pins (pta7?pta0) pta7?pta0 are general-purpose bidirectional input/output (i/o) port pins. see chapter 13 input/output ports for more information. 1.4.10 port b i/o pi ns (ptb7/atd7?ptb0/atd0) port b is an 8-bit special function port that shares all eight pins with the adc. see chapter 3 analog-to-digital converter (adc) and chapter 13 input/output ports for more information. 1.4.11 port c i /o pins (ptc4?ptc0) ptc4 ? ptc3 and ptc1 ? ptc0 are general-purpose bidirectional i/o port pins. ptc2/mclk is a special function port that shares its pin wi th the system clock which has a fr equency equivalent to the system clock. see chapter 13 input/output ports for more information. 1.4.12 port d i/o pins (ptd6?ptd0/atd8) port d is an 7-bit special-function port that shares seven of its pins with the adc and one of its pins with the tim. see chapter 17 timer interface module (tim) , chapter 3 analog-to-digital converter (adc) , and chapter 13 input/output ports for more information. 1.4.13 port e i/o pi ns (pte7/spsck ?pte0/txd) port e is an 8-bit special function port that shares two of its pins with the tim, four of its pins with the spi, and two of its pins with the sci. see chapter 14 serial communications interface (sci) , chapter 16 serial peripheral interface (spi) , chapter 17 timer interface module (tim) , and chapter 13 input/output ports for more information. 1.4.14 port f i/ o pins (ptf3?ptf0/tch2) port f is a 4-bit special function port that shares four of its pins with the tim. see chapter 17 timer interface module (tim) and chapter 13 input/output ports for more information. 1.4.15 bdlc tran smit pin (bdtxd) this pin is the digital output from the bdlc module (bdtxd). see chapter 19 electrical specifications for more information.
general description mc68hc908as32a data sheet, rev. 2.0 26 freescale semiconductor 1.4.16 bdlc r eceive pin (bdrxd) this pin is the digital input to the bdlc module (bdrxd). see chapter 19 electrical specifications for more information. table 1-1. external pins summary pin name function driver type hysteresis (1) 1. hysteresis is not 100% tested but is typically a minimum of 300 mv. reset state pta7?pta0 general-purpose i/o dual state no input hi-z ptb7/atd7?ptb0/atd0 general-purpose i/o adc channel dual state no input hi-z ptc4?ptc0 general-purpose i/o dual state no input hi-z ptd6/atd14/tclk adc channel general-purpose i/o adc channel/timer external input clock dual state no input hi-z ptd5/atd13 adc channel general-purpose i/o adc channel dual state no input hi-z ptd4/atd12 adc channel general-purpose i/o adc channel dual state no input hi-z ptd3/atd11?ptd0/atd8 adc channels general-purpose i/o adc channel dual state no input hi-z pte7/spsck general-purpose i/o spi clock dual state open drain yes input hi-z pte6/mosi general-purpose i/o spi data path dual state open drain yes input hi-z pte5/miso general-purpose i/o spi data path dual state open drain yes input hi-z pte4/ss general-purpose i/o spi slave select dual state yes input hi-z pte3/tch1 general-purpose i/o tim channel 1 dual state yes input hi-z pte2/tch0 general-purpose i/o tim channel 0 dual state yes input hi-z pte1/rxd general-purpose i/o sci receive data dual state yes input hi-z pte0/txd general-purpose i/o sci transmit data dual state no input hi-z ptf3/tch5 general-purpose i/o tim channel 5 dual state yes input hi-z ptf2/tch4 general-purpose i/o tim channel 4 dual state yes input hi-z ptf1/tch3 general-purpose i/o tim channel 3 dual state yes input hi-z ptf0/tch2 general-purpose i/o tim channel 2 dual state yes input hi-z v dd chip power supply n/a n/a n/a v ss chip ground n/a n/a n/a v dda/ v ddaref adc analog power supply cgm analog power supply n/a n/a n/a v ssa /v refl adc ground/adc reference low voltage cgm analog ground n/a n/a n/a v refh a/d reference high voltage n/a n/a n/a osc1 external clock in n/a n/a input hi-z osc2 external clock out n/a n/a output cgmxfc pll loop filter cap n/a n/a n/a irq external interrupt request n/a n/a input hi-z rst reset n/a n/a output low bdrxd bdlc serial input n/a yes input hi-z bdtxd bdlc serial output output no output
pin assignments mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 27 table 1-2. clock signal naming conventions clock signal name description cgmxclk buffered version of osc1 from cgm cgmout pll-based or osc1-bas ed clock output from cgm bus clock cgmout divided by two spsck spi serial clock tclk external clock input for tim table 1-3. clock source summary module clock source adc cgmxclk or bus clock can cgmxclk or cgmout cop cgmxclk cpu bus clock flash bus clock eeprom cgmxclk or bus clock ram bus clock spi bus clock/spsck sci cgmxclk tim bus clock or ptd6/atd14/tclk pit bus clock sim cgmout and cgmxclk irq bus clock brk bus clock lvi bus clock cgm osc1 and osc2
general description mc68hc908as32a data sheet, rev. 2.0 28 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 29 chapter 2 memory 2.1 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 32,256 bytes of flash eeprom 1024 bytes of ram 512 bytes of eeprom with protect option 52 bytes of user-defined vectors 256 bytes of monitor rom 2.2 unimplemented memory locations accessing an unimplemented location can have unpredictable effects on mcu operation. in figure 2-1 and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in figure 2-1 and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. 2.4 input/output (i/o) section addresses $0000?$004f, shown in figure 2-2 , contain the i/o data, status, and control registers. 2.5 additional status and control registers selected addresses in the range $fe00?$ff88 contain additional status and control registers as shown in figure 2-3 . a noted exception is the computer operating pr operly (cop) control register (copctl) at address $ffff. 2.6 vector addr esses and priority addresses in the range $ffda?$ffff contain the user-specified vector locations. the vector addresses are shown in table 2-1 . it is recommended that all vector addresses are defined.
memory mc68hc908as32a data sheet, rev. 2.0 30 freescale semiconductor $0000 $004f i/o registers (80 bytes) $0050 $044f ram (1024 bytes) $0450 $07ff unimplemented (944 bytes) $0800 $09ff eeprom (512 bytes) $0a00 $7fff unimplemented (30,208 bytes) $8000 $fdff flash (32,256 bytes) $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 $fe08 reserved $fe09 configuration write-once regiser 2 (config2) $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (bscr) $fe0f lvi status register (lvisr) $fe10 eeprom eedivh nonvolatile register (eedivhnvr) $fe11 eeprom eedivl nonvolatile register (eedivlnvr) $fe12 $fe19 reserved $fe1a eeprom ee divider high register (eedivh) $fe1b eeprom ee divider low register (eedivl) $fe1c eeprom nonvolatile register (eenvr) $fe1d eeprom control register (eecr) $fe1e reserved $fe1f eeprom array configuration register (eeacr) figure 2-1. memory map
vector addresses and priority mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 31 $fe20 $ff1f monitor rom (256 bytes) $ff20 $ff7f unimplemented (80 bytes) $ff80 flash block protect register (flbpr) $ff81 $ff87 reserved (7 bytes) $ff88 flash control register (flcr) $ff89 $ff8f reserved (6 bytes) $ff90 $ffbf unimplemented (48 bytes) $ffc0 $ffd9 reserved (26 bytes) $ffda $ffff vectors (38 bytes) addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 151. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 153. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 155. read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 157. read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 151. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 2-2. i/o data, status and control registers (sheet 1 of 6) figure 2-1. memory map (continued)
memory mc68hc908as32a data sheet, rev. 2.0 32 freescale semiconductor $0005 data direction register b (ddrb) see page 153. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 155. read: mclken 00 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) see page 158. read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddr2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) see page 159. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 161. read: 0 0 0 0 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset $000a reserved rrrrrrrr $000b reserved rrrrrrrr $000c data direction register e (ddre) see page 160. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d data direction register f (ddrf) see page 162. read: 0 0 0 0 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 $000e reserved rrrrrrrr $000f reserved rrrrrrrr $0010 spi control register (spcr) see page 221. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) see page 223. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) see page 225. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o data, status and control registers (sheet 2 of 6)
vector addresses and priority mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 33 $0013 sci control register 1 (scc1) see page 178. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) see page 180. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) see page 182. read: r8 t8 r r orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) see page 183. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) see page 185. read:000000bkfrpf write: reset:00000000 $0018 sci data register (scdr) see page 186. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) see page 186. read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: reset:00000000 $001a irq status/control register (iscr) see page 139. read: 0 0 0 0 irqf 0 imask mode write: ack reset:00000000 $001b reserved rrrrrrrr $001c pll control register (pctl) see page 106. read: pllie pllf pllon bcs 1111 write: reset:00101111 $001d pll bandwidth control register (pbwc) see page 107. read: auto lock acq xld 0000 write: reset:00000000 $001e pll programming register (ppg) see page 108. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 $001f configuration write-once register (config1) see page 115. read: lvistop r lvirst lvipwr ssrec copl stop copd write: reset:01110000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o data, status and control registers (sheet 3 of 6)
memory mc68hc908as32a data sheet, rev. 2.0 34 freescale semiconductor $0020 tim status and control register (tsc) see page 237. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 reserved rrrrrrrr $0022 tim counter register high (tcnth) see page 238. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0023 tim counter register low (tcntl) see page 238. read:bit 7654321bit 0 write: reset:00000000 $0024 tim modulo register high (tmodh) see page 239. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0025 tim modulo register low (tmodl) see page 239. read: bit 7654321bit 0 write: reset:11111111 $0026 tim channel 0 status and control register (tsc0) see page 240. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0027 tim channel 0 register high (tch0h) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0028 tim channel 0 register low (tch0l) see page 243. read: bit 7654321bit 0 write: reset: $0029 tim channel 1 status and control register (tsc1) see page 240. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $002a tim channel 1 register high (tch1h) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002b tim channel 1 register low (tch1l) see page 243. read: bit 7654321bit 0 write: reset: indeterminate after reset $002c tim channel 2 status and control register (tsc2) see page 240. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o data, status and control registers (sheet 4 of 6)
vector addresses and priority mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 35 $002d tim channel 2 register high (tch2h) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e tim channel 2 register low (tch2l) see page 243. read: bit 7654321bit 0 write: reset: indeterminate after reset $002f tim channel 3 status and control register (tsc3) see page 240. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $0030 tim channel 3 register high (tch3h) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 tim channel 3 register low (tch3l) see page 243. read: bit 7654321bit 0 write: reset: indeterminate after reset $0032 tim channel 4 status and control register (tsc4) see page 240. read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset:00000000 $0033 tim channel 4 register high (tch4h) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 tim channel 4 register low (tch4l) see page 243. read: bit 7654321bit 0 write: reset: indeterminate after reset $0035 tim channel 5 status and control register (tsc5) see page 240. read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 reset:00000000 $0036 tim channel 5 register high (tch5h) see page 243. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 tim channel 5 register low (tch5l) see page 243. read: bit 7654321bit 0 write: reset: indeterminate after reset $0038 adc status and control register (adscr) see page 63. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00000000 $0039 adc data register (adr) see page 65. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o data, status and control registers (sheet 5 of 6)
memory mc68hc908as32a data sheet, rev. 2.0 36 freescale semiconductor $003a adc input clock register (adiclk) see page 65. read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 $003b bdlc analog and roundtrip delay register (bard) see page 85. read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset:11000111 $003c bdlc control register 1 (bcr1) see page 86. read: imsg clks r1 r0 00 ie wcm write: r r reset:11100000 $003d bdlc control register 2 (bcr2) see page 88. read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset:11000000 $003e bdlc state vector register (bsvr) see page 92. read:0 0 i3i2i1i0 0 0 write:rrrrrrrr reset:00000000 $003f bdlc data register (bdr) see page 94. read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: reset: unaffected by reset $0040 $004a reserved rrrrrrrr $004b pit status and control register (psc) see page 147. read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset:00100000 $004c pit counter register high (pcnth) see page 148. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $004d pit counter register low (pcntl) see page 148. read:bit 7654321bit 0 write: reset:00000000 $004e pit counter modulo register high (pmodh) see page 149. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $004f pit counter modulo register low (pmodl) see page 149. read: bit 7654321bit 0 write: reset:11111111 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. i/o data, status and control registers (sheet 6 of 6)
vector addresses and priority mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 37 addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 202. read: rrrrrr bw r write: see note reset: 0 note: writing a 0 clears bw $fe01 sim reset status register (srsr) see page 202. read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 $fe02 reserved rrrrrrrr $fe03 sim break flag control register (sbfcr) see page 203. read: bcferrrrrrr write: reset: 0 $fe09 configuration write-once register (config2) see page 117. read: eedivclk r r r as32a r r r write: reset:00011000 $fe0c break address register high (brkh) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) see page 248. read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) see page 248. read: brke brka 000000 write: reset:00000000 $fe0f lvi status register (lvisr) see page 142. read:lviout0000000 write: reset:00000000 $fe10 eediv high nonvolatile register (eedivhnvr) see page 48. read: write: eediv secd eediv10 eediv9 eediv8 reset: unaffected by reset; $ff when blank $fe11 eediv low nonvolatile register (eedivlnvr) see page 48. read: write: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 reset: unaffected by reset; $ff when blank $fe1a eediv timebase divider high register (eedivh) see page 48. read: write: eediv secd eediv10 eediv9 eediv8 reset: contents of eedivhnvr ($fe10), bits [6:3] = 0 $fe1b eediv timebase divider low register (eedivl) see page 49. read: write: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 reset: contents of eedivlnvr ($fe11) = unimplemented r = reserved figure 2-3. additional status and control registers (sheet 1 of 2)
memory mc68hc908as32a data sheet, rev. 2.0 38 freescale semiconductor $fe1c eeprom nonvolatile register (eenvr) see page 48. read: eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: programmed value or 1 in the erased state $fe1d eeprom control register (eecr) see page 45. read: 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 $fe1f eeprom array configuration register (eeacr) see page 46. read: eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) $ff80 flash block protect register (flbpr) see page 52. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset $ff88 flash control register (flcr) see page 51. read:0000 hven mass erase pgm write: reset:00000000 $ffff cop control register (copctl) see page 121. read: low byte of reset vector write: writing to $ffff clears cop counter reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-3. additional status and control registers (sheet 2 of 2)
vector addresses and priority mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 39 table 2-1. vector addresses vector priority address vector lowest $ffda pit vector (high) $ffdb pit vector (low) $ffdc bdlc vector (high) $ffdd bdlc vector (low) $ffde adc vector (high) $ffdf adc vector (low) $ffe0 sci transmit vector (high) $ffe1 sci transmit vector (low) $ffe2 sci receive vector (high) $ffe3 sci receive vector (low) $ffe4 sci error vector (high) $ffe5 sci error vector (low) $ffe6 spi transmit vector (high) $ffe7 spi transmit vector (low) $ffe8 spi receive vector (high) $ffe9 spi receive vector (low) $ffea tim overflow vector (high) $ffeb tim overflow vector (low) $ffec tim channel 5 vector (high) $ffed tim channel 5 vector (low) $ffee tim channel 4 vector (high) $ffef tim channel 4 vector (low) $fff0 tim channel 3 vector (high) $fff1 tim channel 3 vector (low) $fff2 tim channel 2 vector (high) $fff3 tim channel 2 vector (low) $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) highest $ffff reset vector (low)
memory mc68hc908as32a data sheet, rev. 2.0 40 freescale semiconductor 2.7 random-access memory (ram) the 1024 bytes of random-access memory (ram) are located at address $0050?$044f is the ram location. the 16-bit stack pointer allows the stack ram to be anywhere in the 64 kbyte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 176 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and us er data or code. when the stack pointer is moved from its reset location at $00ff, direct addressi ng mode instructions can access all page zero ram locations efficiently. therefore, page zero ram pr ovides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m68hc05, m6805, and m146805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subroutines. the cpu could overwrite data in the ram during a subroutine or dur ing the interrupt stacking operation. 2.8 electrically erasable progra mmable read-only memory (eeprom) this subsection describes the 512 bytes of electr ically erasable programmable read-only memory (eeprom) residing at address range $0800?$09ff. features include: 512 bytes nonvolatile memory byte, block, or bulk erasable nonvolatile eeprom configurat ion and block protection options on-chip charge pump for programming/erasing security option (1) auto bit driven programming/erasing time feature 2.8.1 functional description the 512 bytes of eeprom are located at $0800?$09 ff and can be programmed or erased without an additional external high voltage supply. the program and erase operations are enabled through the use of an internal charge pump. for each byte of eepr om, the write/erase endur ance is 10,000 cycles. 1. no security feature is absolutely secure . however, freescale?s strategy is to ma ke reading or copying the eeprom difficult for unauthorized users.
electrically erasa ble programmable read-o nly memory (eeprom) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 41 2.8.1.1 eeprom configuration the 8-bit eeprom nonvol atile register (eenvr) and the 16-b it eeprom timebase divider nonvolatile register (eedivnvr) contain the default setti ngs for the following eeprom configurations: eeprom timebase reference eeprom security option eeprom block protection eenvr and eedivnvr are nonvolatile eeprom register s that are programmed and erased in the same way as eeprom bytes. the contents of these register s are loaded into their respective volatile registers during a mcu reset. the values in these read/write volatile registers define the eeprom configurations. for eenvr, the corresponding volatile register is the eeprom array configuration register (eeacr). for the eedivncr (two 8-bit registers: eediv hnvr and eedivlnvr), t he corresponding volatile register is the eeprom divider register (eediv: eedivh and eedivl). 2.8.1.2 eeprom timebase requirements a 35 s timebase is required by the eeprom control circuit for program and erase of eeprom content. this timebase is derived from dividing the cgmxcl k or bus clock (selecte d by eedivclk bit in config2 register) using a timebase divider circuit controlled by t he 16-bit eeprom timebase divider eediv register (eedivh and eedivl). as the cgmxclk or bus clock is user selected, the eeprom timebase divider register must be configured with the appropriate value to obtain the 35 s. the timebase divider value is calculated by using the following formula: eediv= int[reference frequency(hz) x 35 x10 ?6 +0.5] this value is written to the eeprom timebase divi der register (eedivh and eedivl) or programmed into the eeprom timebase divider nonvol atile register prior to any eepro m program or erase operations (see 2.8.1.1 eeprom configuration and 2.8.1.2 eeprom timebase requirements ). 2.8.1.3 eeprom program/erase protection the eeprom has a special feature that designates the 16 bytes of addresses from $08f0?$08ff to be permanently secured. this program/erase protect option is enabled by programming the eeprtct bit in the eeprom nonvolatile register to a 0. once the eeprtct bit is program med to 0 for the first time: programming and erasing of secured loca tions $08f0?$08ff is permanently disabled. secured locations $08f0?$08ff can be read as normal. programming and erasing of eenvr is permanently disabled. bulk and block erase operations are disabl ed for the unprotected locations $0800?$08ef and $0900?$09ff. single byte program and erase operations are still available for locations $0800?$08ef and $0900?$09ff for all bytes that ar e not protected by the eeprom block protect eebpx bits (see 2.8.1.4 eeprom block protection and 2.8.2.2 eeprom array configuration register )
memory mc68hc908as32a data sheet, rev. 2.0 42 freescale semiconductor note once armed, the protect option is permanently enabled. as a consequence, all functions in the eenvr will remain in the state they were in immediately before the security was enabled. 2.8.1.4 eeprom block protection the 512 bytes of eeprom are divided in to four 128-byte blocks. each of these blocks can be protected from erase/program operations by se tting the eebpx bit in the eenvr. table 2-2 shows the address ranges for the blocks. these bits are effective after a reset or a upon read of the eenvr register. the block protect configuration can be modified by erasing/program ming the corresponding bits in the eenvr register and then reading the eenvr register. see 2.8.2.2 eeprom array configuration register for more information. note once eedivsecd in the eedivhnvr is programmed to 0 and after a system reset, the eediv security fe ature is permanently enabled because the eedivsecd bit in the eedivh is always loaded with 0s thereafter. once this security feature is armed, erase and program mode are disabled for eedivhnvr and eedivlnvr. modifications to the eedivh and eedivl registers are also disabled. therefore, be cautious on programming a value into the eedivhnvr. 2.8.1.5 eeprom programming and erasing the unprogrammed or erase state of an eeprom bit is a 1. the factory default for all bytes within the eeprom array is $ff. the programming operation changes an eeprom bit from 1 to 0 (progr amming cannot change a bit from 0 to a 1). in a single programming operation, the minimum eeprom programming size is one bit; the maximum is eight bits (one byte). the erase operation chan ges an eeprom bit from 0 to 1. in a single erase operation, the minimum eeprom erase size is one byte; the maximum is the entire eeprom array. the eeprom can be programmed such that one or mult iple bits are programmed (written to a 0) at a time. however, the user may never program the sa me bit location more than once before erasing the entire byte. in other words, the user is not allowed to program a 0 to a bit that is already programmed (bit state is already 0). for some applications it might be advantageous to track more than 10k events with a single byte of eeprom by programming one bit at a time. for that purpose, a special selective bit programming technique is available. an example of this technique is illustrated in table 2-3 . table 2-2. eeprom array address blocks block number (eebpx) address range eebp0 $0800?$087f eebp1 $0880?$08ff eebp2 $0900?$097f eebp3 $0980?$09ff
electrically erasa ble programmable read-o nly memory (eeprom) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 43 note none of the bit locations are actual ly programmed more than once although the byte was programmed eight times. when this technique is utilized, a program/erase cycl e is defined as multiple program sequences (up to eight) to a unique location followe d by a single erase operation. 2.8.1.6 program/erase using auto bit an additional feature available for eeprom prog ram and erase operations is the auto mode. when enabled, auto mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the eepgm bit. see 2.8.1.7 eeprom programming , 2.8.1.8 eeprom erasing , and 2.8.2.1 eeprom control register for more information. 2.8.1.7 eeprom programming the unprogrammed or erase state of an eeprom bit is a 1. programming changes the state to a 0. only eeprom bytes in the non-protected blocks and the eenvr register can be programmed. use the following procedure to program a byte of eeprom: 1. clear eeras1 and eeras0 and set eelat in the eecr. (a) note if using the auto mode, also set the auto bit during step 1. 2. write the desired data to the desired eeprom address. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for time, t eefpv , for the programming voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bits. (e) note a. eeras1 and eeras0 must be cleared for programming. setting the eelat bit configures the address and data buses to latch data for programming the array. only data with a valid eeprom address will be latched. if eelat is set, other writes to the eecr will be allowed after a valid eeprom write. table 2-3. example selective bit programming description description program data in binary result in binary original state of byte (erased) n/a 1111:1111 first event is recorded by programming bit position 0 1111:1110 1111:1110 second event is recorded by programming bit position 1 1111:1101 1111:1100 third event is recorded by programm ing bit position 2 1111:1011 1111:1000 fourth event is recorded by programming bit position 3 1111:0111 1111:0000 events five through eight are recorded in a similar fashion
memory mc68hc908as32a data sheet, rev. 2.0 44 freescale semiconductor b. if more than one valid eeprom write occurs, the last address and data will be latched overriding the previous address and data. once data is written to the desired address, do not read eeprom locations other than the written location. (reading an eeprom location returns the latched data and causes the read address to be latched). c. the eepgm bit cannot be set if the eelat bit is cleared or a non-valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom locations; otherwise, the current program cy cle will be unsuccessful. when eepgm is set, the on-board programming sequence will be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t eepgm . however, on other mcus, this delay time may be different. for forward compatibility, softwar e should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom array. 2.8.1.8 eeprom erasing the programmed state of an eeprom bit is a 0. eras ing changes the state to a 1. only eeprom bytes in the non-protected blocks and the eenvr register can be erased. use the following procedure to erase a byte, block, or the entire eeprom array: 1. configure eeras1 and eeras0 for byte, block, or bulk erase; set eelat in eecr. (a) note if using the auto mode, also set the auto bit in step 1. 2. byte erase ? write any data to the desired address. (b) block erase ? write any data to an address within the desired block. (b) bulk erase ? write any data to an address within the array. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for a time: t eebyte for byte erase; t eeblock for block erase; t eebulk. for bulk erase. 5. clear eepgm bit. 6. wait for a time, t eefpv , for the erasing voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bits. (e) note a. setting the eelat bit configures t he address and data buses to latch data for erasing the array. only va lid eeprom addresses will be latched. if eelat is set, other writes to th e eecr will be allowed after a valid eeprom write. b. if more than one valid eeprom write occurs, the last address and data will be latched overriding the previous address and data. once data is written to the desired address, do not read eeprom locations other than
electrically erasa ble programmable read-o nly memory (eeprom) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 45 the written location. (reading an eeprom location returns the latched data and causes the read address to be latched). c. the eepgm bit cannot be set if the eelat bit is cleared or a non-valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom locations; otherwise, the current program cy cle will be unsuccessful. when eepgm is set, the on-board programming sequence will be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t eebyte /t eeblock /t eebulk . however, on other mcus, this delay time may be different. for forward compat ibility, software should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom array. 2.8.2 eeprom regi ster descriptions four i/o registers and three nonvolatile registers co ntrol program, erase, and options of the eeprom array. 2.8.2.1 eeprom control register this read/write register controls programming/erasing of the array. bit 7? unused bit this read/write bit is software programmable but has no functionality. eeoff ? eeprom power down this read/write bit disables the eeprom module for lower power consumption. any attempts to access the array will give unpredict able results. reset clears this bit. 1 = disable eeprom array 0 = enable eeprom array eeras1 and eeras0 ? erase/program mode select bits these read/write bits set the eras e modes. reset clears these bits. address: $fe1d bit 7654321bit 0 read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 = unimplemented figure 2-4. eeprom control register (eecr)
memory mc68hc908as32a data sheet, rev. 2.0 46 freescale semiconductor eelat ? eeprom latch control this read/write bit latches the address and data buses for programming the eeprom array. eelat cannot be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom programming or erase operation 0 = buses configured for normal operation auto ? automatic termination of program/erase cycle when auto is set, eepgm is cleared automatically a fter the program/erase cy cle is terminated by the internal timer. see note d for 2.8.1.7 eeprom programming , 2.8.1.8 eeprom erasing , and 19.11.2 eeprom memory characteristics . 1 = automatic clear of eepgm is enabled 0 = automatic clear of eepgm is disabled eepgm ? eeprom program/erase enable this read/write bit enables the internal charge pump and applies the programming/erasing voltage to the eeprom array if the eelat bit is set and a wr ite to a valid eeprom location has occurred. reset clears the eepgm bit. 1 = eeprom programming/erasing power switched on 0 = eeprom programming/erasing power switched off note writing 0s to both the eelat and eepgm bi ts with a single instruction will clear eepgm only to allow time for the removal of high voltage. 2.8.2.2 eeprom array configuration register the eeprom array configuration register confi gures eeprom security and eeprom block protection. this read-only register is loaded with the contents of the eeprom nonvolatile register (eenvr) after a reset. bit 7?5 ? unused bits these read/write bits are software programmable but have no functionality. table 2-4. eeprom program/erase mode select eebpx eeras1 eeras0 mode 0 0 0 byte program 0 0 1 byte erase 0 1 0 block erase 0 1 1 bulk erase 1 x x no erase/program x = don?t care address: $fe1f bit 7 6 5 4 3 2 1 bit 0 read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) = unimplemented figure 2-5. eeprom array co nfiguration register (eeacr)
electrically erasa ble programmable read-o nly memory (eeprom) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 47 eeprtct ? eeprom protection bit the eeprtct bit is used to enable the security feature in the eeprom (see 2.8.1.3 eeprom program/erase protection ). 1 = eeprom security disabled 0 = eeprom security enabled note this feature is a write-once feature. once the protection is enabled it may not be disabled. eebp[3:0] ? eeprom block protection bits these bits prevent blocks of eeprom array from being programmed or erased. 1 = eeprom array block is protected 0 = eeprom array block is unprotected block number (eebpx) address range eebp0 $0800?$087f eebp1 $0880?$08ff eebp2 $0900?$097f eebp3 $0980?$09ff table 2-5. eeprom block protect and security summary address range eebpx eeprtct = 1 eeprtct = 0 $0800?$087f eebp0 = 0 byte programming available bulk, block, and byte erasing available byte programming available only byte erasing available eebp0 = 1 protected protected $0880?$08ef eebp1 = 0 byte programming available bulk, block, and byte erasing available byte programming available only byte erasing available eebp1 = 1 protected protected $08f0?$08ff eebp1 = 0 byte programming available bulk, block, and byte erasing available secured (no programming or erasing) eebp1 = 1 protected $0900? $097f eebp2 = 0 byte programming available bulk, block, and byte erasing available byte programming available only byte erasing available eebp2 = 1 protected protected $0980?$09ff eebp3 = 0 byte programming available bulk, block, and byte erasing available byte programming available only byte erasing available eebp3 = 1 protected protected
memory mc68hc908as32a data sheet, rev. 2.0 48 freescale semiconductor 2.8.2.3 eeprom nonvolatile register the contents of this register is loaded into the eeprom array configuration register (eeacr) after a reset. this register is erased and programm ed in the same way as an eeprom byte. (see 2.8.2.1 eeprom control register for individual bit descriptions). note the eenvr will leave the factory programmed with $f0 such that the full array is available and unprotected. 2.8.2.4 eeprom timebase divider register the 16-bit eeprom timebase divider register consists of two 8-bit registers: eedivh and eedivl. the 11-bit value in this register is used to configur e the timebase divider circuit to obtain the 35 s timebase for eeprom control. these two read/write register s are respectively loaded with the contents of the eeprom timebase divider nonvolatile register s (eedivhnvr and eedivlnvr) after a reset. eedivsecd ? eeprom divider security disable this bit enables/disables the security feature of the eediv registers. when eediv security feature is enabled, the state of the registers eedivh and eedivl are locked (including eedivsecd bit). the eedivhnvr and eedivlnvr nonvolatile memory registers are also protected from being erased/programmed. 1 = eediv security feature disabled 0 = eediv security feature enabled address: $fe1c bit 7 6 5 4 3 2 1 bit 0 read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: pv pv = programmed value or 1 in the erased state. figure 2-6. eeprom nonvolatile register (eenvr) address: $fe1a bit 7 6 5 4 3 2 1 bit 0 read: eediv secd 0000 eediv10 eediv9 eediv8 write: reset: contents of eedivhnvr ($fe10), bits [6:3] = 0 = unimplemented figure 2-7. eediv divider high register (eedivh) address: $fe1b bit 7 6 5 4 3 2 1 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of eedivlnvr ($fe11) figure 2-8. eediv divider low register (eedivl)
electrically erasa ble programmable read-o nly memory (eeprom) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 49 eediv[10:0] ? eeprom timebase prescaler these prescaler bits store the value of eediv whic h is used as the divisor to derive a timebase of 35 s from the selected reference clock source (cgmxc lk or bus block in the config2 register) for the eeprom related internal timer and circuits. eediv[10:0] bits are readable at any time. they are writable when eelat = 0 and eedivsecd = 1. the eediv value is calculated by the following formula: eediv= int[reference frequency(hz) x 35 x10 ?6 +0.5] where the result inside the bracket is rounded down to the nearest integer value for example, if the reference frequency is 4.9152 mhz, the eediv value is 172 note programming/erasing the eeprom with an improper eediv value may result in data lost and reduc e endurance of the eeprom device. 2.8.2.5 eeprom timebase divider nonvolatile register the 16-bit eeprom timebase divider n onvolatile register consists of two 8-bit registers: eedivhnvr and eedivlnvr. the contents of these two register s are respectively loaded into the eeprom timebase divider registers, eedivh and eedivl, after a reset. these two registers are erased and programmed in the same way as an eeprom byte. these two registers are protected from erase and program operations if eedivsecd is set to 1 in eedivh (see 2.8.2.4 eeprom timebase divider register ) or programmed to a 1 in the eedivhnvr. note once eedivsecd in the eedivhnvr is programmed to 0 and after a system reset, the eediv security fe ature is permanently enabled because the eedivsecd bit in the eedivh is always loaded with 0s thereafter. once this security feature is armed, erase and program mode are disabled for eedivhnvr and eedivlnvr. modifications to the eedivh and eedivl registers are also disabled. t herefore, care should be taken before programming a value into the eedivhnvr. address: $fe10 bit 7 6 5 4 3 2 1 bit 0 read: eedivs- ecd r r r r eediv10 eediv9 eediv8 write: reset: unaffected by reset; $ff when blank r=reserved figure 2-9. eeprom divider nonvolatile register high (eedivhnvr)) address: $fe11 bit 7 6 5 4 3 2 1 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank figure 2-10. eeprom divider nonvolatile register low (eedivlnvr)
memory mc68hc908as32a data sheet, rev. 2.0 50 freescale semiconductor 2.8.3 low-power modes the wait and stop instructions can put the mcu in low power-consumption standby modes. 2.8.3.1 wait mode the wait instruction does not affect the eeprom. it is possible to start the program or erase sequence on the eeprom and put the mcu in wait mode. 2.8.3.2 stop mode the stop instruction reduces t he eeprom power consumption to a minimum. the stop instruction should not be executed while a programm ing or erasing sequence is in progress. if stop mode is entered while eelat and eepgm ar e set, the programming sequence will be stopped and the programming voltage to the eeprom arra y removed. the programming sequence will be restarted after leaving stop mode; access to the eeprom is only possible after the programming sequence has completed. if stop mode is entered while eelat and eepgm is cleared, the programming sequence will be terminated abruptly. in either case, the data integrity of the eeprom is not guaranteed. 2.9 flash memory (flash) this subsection describes the o peration of the embedded flash memo ry. this memory can be read, programmed, and erased from a single external su pply. the program and erase operations are enabled through the use of an internal charge pump. the flash memory is an array of 32,256 bytes with one byte of block prot ection and an additional 38 bytes of user vectors. an erased bit reads as a 1 and a programmed bit reads as a 0. memory in the flash array is organized into rows within pages. there are two rows of memory per page with 64 bytes per row. the minimum erase block size is a single page,128 bytes. programming is performed on a per-row basis, 64 bytes at a time. pr ogram and erase operations are facilitated through control bits in the flash control register (flcr). details for these operations appear later. the flash memory map consists of: $8000?$fdff ? user memory (32,256 bytes) $ff80 ? flash block protect register (flbpr) $ff88 ? flash control register (flcr) $ffcc?$ffff ? these locations are reserved for user-defined interrupt and reset vectors programming tools are available from freescale. cont act your local freescale representative for more information. note a security feature prevents viewing of the flash contents. (1) 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
flash memory (flash) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 51 2.9.1 flash control and block protect registers the flash array has two registers that control its operation, the flash control register (flcr) and the flash bock protect register (flbpr). 2.9.1.1 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the flash array for mass or page erase operation. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be set at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected address: $ff88 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-11. flash control register (flcr)
memory mc68hc908as32a data sheet, rev. 2.0 52 freescale semiconductor 2.9.1.2 flash block protect register the flash block protect register (flbpr) is impl emented as a byte within the flash memory and therefore can only be written during a flash progr amming sequence. the value in this register determines the starting location of the protected range within the flash memory. flbpr[7:0] ? block protect register bits [7:0] these eight bits represent bits [14:7] of a 16-bit memory address. bit 15 is 1 and bits [6:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. flash is protected from this start address to the end of flash memory at $ffff. with this mechanism, the protect start address can be $xx00 and $xx80 (128 byte page boundaries) within the flash array. figure 2-13. flash block protect start address decreasing the value in flbpr by one increases the protected range by one page (128 bytes). however, programming the block protect register with $fe protects a range twice that size, 256 bytes, in the corresponding array. $fe means that location s $ff00?$ffff are protected in flash. see table 2-6 . the flash memory does not exist at some location s. the block protection range configuration is unaffected if flash memory does not exist in that range. refer to the memory map ( figure 2-1 ) and make sure that the desired locations are protected. address: $ff80 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:uuuuuuuu u = unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-12. flash block protect register (flbpr) 0 0 0 0 0 1 1 flbpr value start address of flash block protect 0
flash memory (flash) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 53 2.9.2 flash bl ock protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made fo r protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protec tion is done by using the flash block protection register (flbpr). flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit can not be set in either erase or program operations. note in performing a program or erase operation, flbpr must be read after setting the pgm or erase bit and before asserting the hven bit. when the flbpr is programmed with all 0s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1s), the entire memory is accessible for program and erase. when bits within flbpr are programmed (0s), they lock a block of memory address ranges as shown in 2.9.1.2 flash block protect register . if flbpr is programmed with any value other than $ff, the protected block of flash memory can not be erased or programmed. note the vector locations and the flbpr are located in the same page. flbpr is not protected with special hardware or software; therefore, if this page is not protected by flbpr and the vector locations are erased by either a page or a mass erase operation, flbpr will also be erased. table 2-6. flash protected ranges flbpr[7:0] protected range $ff no protection $fe $ff00 ? $ffff $fd $fe80 ? $ffff $0b $8580 ? $ffff $0a $8500 ? $ffff $09 $8480 ? $ffff $08 $8400 ? $ffff $04 $8200 ? $ffff $03 $8180 ? $ffff $02 $8100 ? $ffff $01 $8080 ? $ffff $00 $8000 ? $ffff
memory mc68hc908as32a data sheet, rev. 2.0 54 freescale semiconductor 2.9.3 flash page erase operation use this step-by-step procedure to erase a page (128 bytes) of flash memory to read as a 1: 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. caution a page erase of the vector page will erase the internal oscillator trim value at $ffc0. in applications that require more than 1000 program /erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.
flash memory (flash) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 55 2.9.4 flash m ass erase operation use this step-by-step procedure to erase the entire flash memory to read as a 1: 1. set both the erase bit and the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t merase (minimum 4 ms). 7. clear the erase and mass bits. note mass erase is disabled whenever any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvhl (minimum 100 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. 2.9.5 flash program operation programming of the flash memory is done on a row basi s. a row consists of 64 consecutive bytes with address ranges as follows: $xx00 to $xx3f $xx40 to $xx7f $xx80 to $xxbf $xxc0 to $xxff during the programming cycle, make sure that all addr esses being written to fit within one of the ranges specified above. attempts to program addresses in different row ranges in one programming cycle will fail. use this step-by-step procedure to program a row of flash memory. note 1. when in monitor mode, with security sequence failed (see 18.3.2 security ), write to the flash block protect register in- stead of any flash address.
memory mc68hc908as32a data sheet, rev. 2.0 56 freescale semiconductor in order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read the flash block protect register. 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum 5 s). 7. write data to the flash address being programmed (1) . 8. wait for time, t prog (minimum 30 s). 9. repeat step 7 and 8 until all desir ed bytes within the row are programmed. 10. clear the pgm bit (1) . 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. the flash programming algorithm flowchart is shown in figure 2-14 . note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. however, care must be taken to ensure that these operations do not access any address within the flash array memory space such as the cop control register at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. d. do not exceed t prog maximum or t hv maximum. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv max. please also see 19.11.3 flash memory characteristics . e. the time between each flash address change (step 7 to step 7), or the time between the last flash address programmed to clearing the pgm bit (step 7 to step 10) must not exceed t prog maximum. f. be cautious when programming the flash array to ensure that non-flash locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. this applies particularly to $ffda?$ffff (38 bytes) 1. the time between each flash address ch ange, or the time between the last fl ash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum.
flash memory (flash) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 57 figure 2-14. flash programming algorithm flowchart set hven bit read the flash block wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7 to step 7), or must not exceed the maximum programming time, t prog maximum. the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) notes: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory this row program algorit hm assumes the row/s to be programmed are initially erased. protect register write any data to any flash address within the row address range desired
memory mc68hc908as32a data sheet, rev. 2.0 58 freescale semiconductor 2.9.6 low-power modes the wait and stop instructions will place the mcu in low power-consumption standby modes. 2.9.6.1 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash. wait mode will suspend any flash progra m/erase operations and leave the memory in a standby mode. 2.9.6.2 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash. stop mode will suspend any flash program/erase operations and leave the memory in a standby mode. note standby mode is the power saving mode of the flash module, in which all internal control signals to the flash are inactive and the current consumption of the flash is minimum.
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 59 chapter 3 analog-to-digital converter (adc) 3.1 introduction this section describes the analog-to-digital conver ter (adc). the adc is an 8-bit analog-to-digital converter. for further information regarding analog-to-digital converters on freescale microcontrollers, please consult the hc08 adc reference manual , freescale document order number adcrm/ad. 3.2 features features include: 15 channels with multiplexed input linear successive approximation 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 3.3 functional description fifteen adc channels are available for sa mpling external sources at pins ptd6/atd14/taclk ? ptd0/atd8 and ptb7/atd7 ? ptb0/atd0. an analog multiplexer allows the single adc converter to select one of 15 adc channels as adc voltage in (adcvin). adcvin is converted by the successive approximation registe r-based counters. when the c onversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 3-2 . 3.3.1 adc port i/o pins ptd6/atd14/taclk ? ptd0/atd8 and ptb7/atd7 ? ptb0/atd0 are general- purpose i/o pins that share with the adc channels. the channel select bits define which adc channel/p ort pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as in put to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a 0 if t he corresponding ddr bit is at 0. if t he ddr bit is at 1, the value in the port data latch is read. note do not use adc channels atd14 or atd12 when using the ptd6/atd14/taclk or ptd4/atd12/tbclk pins as the clock inputs for the 16-bit timers.
analog-to-digital converter (adc) mc68hc908as32a data sheet, rev. 2.0 60 freescale semiconductor figure 3-1. block diagram highlighting adc block and pins 3.3.2 voltage conversion when the input voltage to the adc equals v refh (see 19.7 analog-to-digital converter (adc) characteristics ), the adc converts the signal to $ff (full scale). if the input voltage equals v ssa, the adc converts it to $00. input voltages between v refh and v ssa are a straight-line linear conversion. conversion accuracy of al l other input voltages is not guaranteed. avoid current injection on unused adc inputs to prevent potential conversion error. note input voltage should not exceed the analog supply voltages. break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 61 figure 3-2. adc block diagram 3.3.3 conversion time conversion starts after a write to the adscr (adc status control register, $0038), and requires between 16 and 17 adc clock cycles to complete. conversion time in terms of the number of bus cycles is a function of adiclk select, cgmxclk frequency, bus frequency, and adiv prescaler bits. for example, with a cgmxclk frequency of 4 mhz, bus frequency of 8 mhz, and fixed adc clock frequency of 1 mhz, one conversion will take between 16 and 17 s and there will be between 128 bus cycles between each conversion. sample rate is approximately 60 khz. refer to 19.7 analog-to-digital converter (adc) characteristics . 3.3.4 continuous conversion in the continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not. internal data bus read ddrb/ddrb write ddrb/ddrd reset write ptb/ptd read ptb/ptd ptbx/ptdx ddrbx/ddrdx ptbx/ptdx interrupt logic channel select adc clock generator conversion complete adc voltage in (adcvin) adc clock cgmxclk bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x 16 to 17 adc clock cycles conversion time = ???????????? adc clock frequency number of bus cycles = c onversion time x bus frequency
analog-to-digital converter (adc) mc68hc908as32a data sheet, rev. 2.0 62 freescale semiconductor conversions will continue until the adco bit (adc status control register, $0038) is cleared. the coco bit is set after the first conversion and will stay set for the next several conversions until the next write of the adc status and control register or the next read of the adc data register. 3.3.5 accuracy and precision the conversion process is monotoni c and has no missing codes. see 19.7 analog-to-digital converter (adc) characteristics for accuracy information. 3.4 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. if the coco bit is set, an interrupt is generated. the coco bit is not used as a conversion complete flag when interrupts are enabled. 3.5 low-power modes the following subsections des cribe the low-power modes. 3.5.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the adch[4:0] bits in the adc status and control register before executing the wait instruction. 3.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 3.6 i/o signals the adc module has 15 channels that are shared with i/o ports b and d. refer to 19.7 analog-to-digital converter (adc) characteristics for voltages referenced below. 3.6.1 adc analog power pin (v ddaref )/adc voltage reference pin (v refh ) the adc analog portion uses v ddaref as its power pin. connect the v dda /v ddaref pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddaref for good results. v refh is the high reference voltage for all analog-to-digital conversions. note route v ddaref carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. v ddaref must be present for operation of the adc.
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 63 3.6.2 adc analog ground pin (v ssa )/adc voltage refe rence low pin (v refl ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same voltage potential as v ss . v refl is the lower reference supply for the adc. 3.6.3 adc voltage in (adcvin) adcvin is the input voltage signal from one of the 15 adc channels to the adc module. 3.7 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc clock register (adiclk) 3.7.1 adc status and control register the following paragraphs describe the functi on of the adc status and control register. coco ? conversions complete bit when the aien bit is a 0, the coco is a read-only bit which is set each time a conversion is completed. this bit is cleared whenever the adc status and cont rol register is written or whenever the adc data register is read. if the aien bit is a 1, the coco is a read/write bi t which selects the cpu to service the adc interrupt request. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conver sion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion address: $0038 bit 7654321bit 0 read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: r reset:00011111 r= reserved figure 3-3. adc status and control register (adscr)
analog-to-digital converter (adc) mc68hc908as32a data sheet, rev. 2.0 64 freescale semiconductor adch[4:0] ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 form a 5-bi t field which is used to select one of 15 adc channels. channel selection is detailed in the followin g table. care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. see table 3-1 . the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when t he adc is not used. reset sets these bits. note recovery from the disabled state requi res one conversion cycle to stabilize. table 3-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptd0/atd8/atd8 01001 ptd1/atd9/atd9 01010ptd2/atd10/atd10 01011ptd3/atd11/atd11 0 1 1 0 0 ptd4/atd12/tbclk/atd12 01101ptd5/atd13/atd13 01110ptd6/atd14/taclk/atd14 range 01111 ($0f) to 11010 ($1a) unused (1) 1. if any unused channels are selected, the resulting adc conversion will be unknown. 11011 reserved 11100 unused (1) 11101 v refh (2) 2. the voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the adc converter both in production test and for user applications. 11110 v ssa /v refl (2) 11111 [adc power off]
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 65 3.7.2 adc data register one 8-bit result register is provided. this regi ster is updated each time an adc conversion completes. 3.7.3 adc input clock register this register selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field which se lects the divide ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock confi gurations. the adc clock should be set to approximately 1 mhz. address: $0039 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 3-4. adc data register (adr) address: $003a bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 = unimplemented figure 3-5. adc input clock register (adiclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care
analog-to-digital converter (adc) mc68hc908as32a data sheet, rev. 2.0 66 freescale semiconductor adiclk ? adc input clock register bit adiclk selects either bus clock or cgmxclk as t he input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less t han 1 mhz, use the pll-generated bus clock as the clock source. as long as the internal adc clock is at approximately 1 mhz, correct operation can be guaranteed. see 19.7 analog-to-digital converter (adc) characteristics . 1 = internal bus clock 0 = external clock (cgmxclk) note during the conversion process, changi ng the adc clock will result in an incorrect conversion. f xclk or bus frequency 1 mhz = ??????????? adiv[2:0]
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 67 chapter 4 byte data link controller (bdlc) 4.1 introduction the byte data link controller (bdlc) provides access to an external serial communication multiplex bus, operating according to the society of au tomotive engineers ( sae) j1850 protocol. 4.2 features features include: sae j1850 class b data communications network in terface compatible and is o compatible for low speed (< 125 kbps) serial data communications in automotive applications 10.4 kbps variable pulse width (vpw) bit format digital noise filter collision detection hardware cyclical redundancy chec k (crc) generation and checking two power-saving modes with autom atic wakeup on network activity polling and cpu interrupts available block mode receive and transmit supported supports 4x receive mode, 41.6 kbps digital loopback mode analog loopback mode in-frame response (ifr) types 0, 1, 2, and 3 supported 4.3 functional description figure 4-2 shows the organization of the bdlc module. the cpu interface contains the software addressable registers and provides the link between the cpu and the buffers. the buffers provide storage for data received and data to be transmitted onto the j1850 bus. the protocol handler is responsible for the encoding and decoding of data bits and special message symbols during trans mission and reception. the mux interface provides the link between the bdlc digital section and the analog physical interface. the wave shaping, driving, and digitizing of data is performed by the physical interface. use of the bdlc module in mess age networking fully implements the sae standard j1850 class b data communication network interface specification. note it is recommended that the reader be familiar with the sae j1850 document and iso serial communication docum ent prior to proceeding with this section.
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 68 freescale semiconductor figure 4-1. block diagram highlighting bdlc block and pins break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 69 figure 4-2. bdlc block diagram 4.3.1 bdlc operating modes the bdlc has five main modes of operation which interact with the power supplies, pins, and the remainder of the mcu as shown in figure 4-3 . figure 4-3. bdlc operating modes state diagram cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc v dd > v dd (minimum) and power off reset bdlc stop run v dd v dd (minimum) stop instruction or (from any mode) bdlc wait network activity or wait instruction and wcm = 1 wait instruction and wcm = 0 any mcu reset source asserted no mcu reset source asserted any mcu reset source asserted network activity or other mcu wakeup other mcu wakeup cop, illaddr, pu, reset, lvr, por
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 70 freescale semiconductor 4.3.1.1 power off mode this mode is entered from reset mode whenever the bdlc supply voltage, v dd , drops below its minimum specified value for the bdlc to guarantee operati on. the bdlc will be placed in reset mode by low-voltage reset (lvr) before being powered down. in th is mode, the pin input and output specifications are not guaranteed. 4.3.1.2 reset mode this mode is entered from the power off mode whenever the bdlc supply voltage, v dd , rises above its minimum specified value (v dd ?10%) and some mcu reset source is asserted. the internal mcu reset must be asserted while powering up the bdlc or an unknown state will be entered and correct operation cannot be guaranteed. reset mode is also entered from any other mode as soon as one of the mcu?s possible reset sources (such as lvr, por, cop watchdog, and reset pin, etc.) is asserted. in reset mode, the internal bdlc voltage references are operative; v dd is supplied to the internal circuits which are held in their reset state; and the internal bd lc system clock is runni ng. registers will assume their reset condition. outputs are held in their pr ogrammed reset state. therefore, inputs and network activity are ignored. 4.3.1.3 run mode this mode is entered from the reset mode after al l mcu reset sources are no longer asserted. run mode is entered from the bdlc wait mode whenever activity is sensed on the j1850 bus. run mode is entered from the bdlc stop mode whenever network activity is sensed, although messages will not be received properly until the clocks ha ve stabilized and the cpu is in run mode also. in this mode, normal network operation takes place. the user should ensure that all bdlc transmissions have ceased before exiting this mode. 4.3.1.4 bdlc wait mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a wait instruction and if the wcm bit in the bcr1 register is cleared previously. in this mode, the bdlc internal clocks continue to run. the first passive-to-ac tive transition of the bus generates a cpu interrupt request from the bdlc which wakes up the bdlc and the cpu. in addition, if the bdlc receives a valid eof symbol while oper ating in wait mode, then the bdlc also will generate a cpu interrupt request which wakes up the bdlc and the cpu. see 4.7.1 wait mode . 4.3.1.5 bdlc stop mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait inst ruction and the wcm bit in the bcr1 register is set previously. in this mode, the bdlc internal clocks are stopped but the physical interface circuitry is placed in a low-power mode and awaits network activity. if network activity is sensed, then a cpu interrupt request will be generated, restarting the bdlc internal clocks. see 4.7.2 stop mode .
bdlc mux interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 71 4.3.1.6 digital loopback mode when a bus fault has been detected, the digital loopbac k mode is used to determine if the fault condition is caused by failure in the node?s internal circuits or elsewhere in the network, including the node?s analog physical interface. in this mode, the transmit digita l output pin (bdtxd) and the receive digital input pin (bdrxd) of the digital interface are disconnected from the analog physical interface and tied together to allow the digital portion of the bdlc to transmit and receive its own messages without driving the j1850 bus. 4.3.1.7 analog loopback mode analog loopback is used to determine if a bus fault has been caused by a failure in the node?s off-chip analog transceiver or elsewhere in the network. the bcld analog loopback m ode does not modify the digital transmit or receive functions of the bd lc. it does, however, ensure that once analog loopback mode is exited, the bdlc will wait for an idle bus condition before participation in network communication resumes. if the off-chip analog transceiver has a loo pback mode, it usually causes the input to the output drive stage to be looped back into the receiver, allowing the node to receive messages it has transmitted without driving the j1850 bus. in this mode, the output to the j1850 bus is typi cally high impedance. this allows the communication path through the analog trans ceiver to be tested without interfering with network activity. using the bdlc analog loopback mode in conjunction with the analog transceiver?s loopback mode ensures that, once the off-chip anal og transceiver has exited loopback mode, the bcld will not begin communicating before a kn own condition exists on the j1850 bus. 4.4 bdlc mux interface the mux interface is responsible for bit encoding/dec oding and digital noise filtering between the protocol handler and the physical interface. figure 4-4. bdlc block diagram cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 72 freescale semiconductor 4.4.1 rx digital filter the receiver section of the bdlc includes a digital lo w-pass filter to remove narrow noise pulses from the incoming message. an outline of the digital filter is shown in figure 4-5 . figure 4-5. bdlc rx digital filter block diagram 4.4.1.1 operation the clock for the digital filter is pr ovided by the mux interface clock (see f bdlc parameter in table 4-3 ). at each positive edge of the clock signal, the current state of the receiver physical interface (bdrxd) signal is sampled. the bdrxd signal state is used to determine whether the counter should increment or decrement at the next negat ive edge of the clock signal. the counter will increment if the input data sample is high but decrement if the input sample is low. therefore, the counter will thus progress either up toward 15 if, on average, the bdrxd signal remains high or progress down toward 0 if, on average, the bdrxd signal remains low. when the counter eventually reaches the value 15, the digital filter decides that the condition of the bdrxd signal is at a stable logic level 1 and the data latch is set, causing the filtered rx data signal to become a logic level 1. furthermore, the counter is prevented from overflowing and can only be decremented from this state. alternatively, should the counter even tually reach the value 0, the digita l filter decides that the condition of the bdrxd signal is at a stable logic level 0 and t he data latch is reset, causing the filtered rx data signal to become a logic level 0. furthermore, t he counter is prevented from underflowing and can only be incremented from this state. the data latch will retain its value until the count er next reaches the opposite end point, signifying a definite transition of the signal. 4.4.1.2 performance the performance of the digital filter is best descri bed in the time domain rather than the frequency domain. if the signal on the bdrxd signal transitions, then there will be a delay before that transition appears at the filtered rx data output signal. this delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling point s. this filter delay must be taken into account when performing message arbitration. 4-bit up/down couter data up/down out d q input dq latch sync filtered rx data out rx data from physical interface (bdrxd) mux interface clock
bdlc mux interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 73 for example, if the frequency of the mux interface clock (f bdlc ) is 1.0486 mhz, then the period (t bdlc ) is 954 ns and the maximum filter delay in the absence of noise will be 15.259 s. the effect of random noise on the bdrxd signal depends on the characteristics of the noise itself. narrow noise pulses on the bdrxd signal will be ignored comple tely if they are shorter than the filter delay. this provides a degree of low-pass filtering. if noise occurs during a symbol transition, the dete ction of that transition can be delayed by an amount equal to the length of the noise burst. this is just a reflection of the uncertainty of where the transition is truly occurring within the noise. noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length, will be detected by the next stage of th e bdlc?s receiver as an invalid symbol. noise pulses that are longer than the shortest allo wable symbol length will be detected normally as an invalid symbol or as invalid dat a when the frame?s crc is checked. 4.4.2 j1850 frame format all messages transmitted on the j1850 bus are structured using the format shown in figure 4-6 . j1850 states that each message has a maximum length of 101 pwm bit times or 12 vpw bytes, excluding sof, eod, nb, and eof, with each byte transmitted msb first. all vpw symbol lengths in the following descripti ons are typical values at a 10.4 kbps bit rate. sof ? start-of-frame symbol all messages transmitted onto the j1850 bus must begin with a long-active 200- s period sof symbol. this indicates the start of a new message transmi ssion. the sof symbol is not used in the crc calculation. data ? in-message data bytes the data bytes contained in the message include the message priority/type, message id byte (typically the physical address of the responder), and any ac tual data being transmitted to the receiving node. the message format used by the bdlc is similar to the 3-byte consolidated header message format outlined by the sae j1850 document. see sae j1850 ? class b data communications network interface for more information about 1- and 3-byte headers. messages transmitted by the bdlc onto the j1850 bus must contain at least one data byte and, therefore, can be as short as one data byte and on e crc byte. each data byte in the message is eight bits in length and is transmitted msb to lsb. crc ? cyclical redundancy check byte this byte is used by the receiver(s) of each mess age to determine if any errors have occurred during the transmission of the message. the bdlc calculates the crc byte and appends it onto any messages transmitted onto the j 1850 bus. it also performs crc detection on any messages it receives from the j1850 bus. data e o d optional i f s idle sof priority (data0) message id (data1) data n crc n b ifr eof idle figure 4-6. j1850 bus message format (vpw)
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 74 freescale semiconductor crc generation uses the divisor polynomial x 8 + x 4 + x 3 + x 2 + 1. the remainder polynomial initially is set to all ones. each byte in the message after t he start of frame (sof) symbol is processed serially through the crc generation circuitry. the one?s complement of the remainder then becomes the 8-bit crc byte, which is appended to the message after the data bytes in msb-to-lsb order. when receiving a message, the bdlc uses the same di visor polynomial. all data bytes, excluding the sof and end of data symbols (eod) but including the crc byte, are used to check the crc. if the message is error free, the remainder polynomial will equal x 7 + x 6 + x 2 = $c4, regardless of the data contained in the message. if the calculated crc does not equal $c4, the bdlc will recognize this as a crc error and set the crc error flag in the bsvr. eod ? end-of-data symbol the eod symbol is a long 200- s passive period on the j1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. no flag is set upon reception of the eod symbol. ifr ? in-frame response bytes the ifr section of the j1850 message format is optiona l. users desiring further definition of in-frame response should review the sae j1850 ? class b data communi cations networ k interface specification. eof ? end-of-frame symbol this symbol is a long 280- s passive period on the j1850 bus and is longer than an end-of-data (eod) symbol, which signifies the end of a message. since an eof symbol is longer than a 200- s eod symbol, if no response is transmitted after an eo d symbol, it becomes an eof, and the message is assumed to be completed. the eof flag is set upon receiving the eof symbol. ifs ? inter-frame separation symbol the ifs symbol is a 20- s passive period on the j1850 bus which allows proper synchronization between nodes during continuous message transmiss ion. the ifs symbol is transmitted by a node after the completion of the end-of-frame (eof) period and, therefore, is seen as a 300- s passive period. when the last byte of a message has been transmitt ed onto the j1850 bus and the eof symbol time has expired, all nodes then must wait for the ifs symbol time to expire before transmitting a start-of-frame (sof) symbol, marking the beginning of another message. however, if the bdlc is waiting for the ifs peri od to expire before beginning a transmission and a rising edge is detected before the ifs time has expired, it will synchronize internally to that edge. if a write to the bdr register (for instance, to initiate transmission) occurred on or before 104 t bdlc from the received rising edge, then the bdlc will transmit and arbitrate for the bus. if a cpu write to the bdr register occurred after 104 t bdlc from the detection of the rising edge, then the bdlc will not transmit, but will wait for the ne xt ifs period to expire before attempting to transmit the byte. a rising edge may occur during the ifs period because of varying clock tolerances and loading of the j1850 bus, causing different nodes to observe the comp letion of the ifs period at different times. to allow for individual clock tolerances, receivers mu st synchronize to any sof occurring during an ifs period. note if two messages are received with a 300 s ( 1 s ) interframe separation (ifs) as measured at the rx pin, the start-of-frame (sof) symbol of the second message will generate an invalid symbol interrupt. this interrupt results in the second message being lost and will therefore be unavailable
bdlc mux interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 75 to the application software. implement ations of this bdlc design on silicon have not been exposed to interframe separation rates faster than 320 s in practical application and have therefore previously not exhibited this behavior. ensuring that no nodes on the j1850 network transmit messages at 300 s ( 1 s ) ifs will avoid this missed message frame. in addition, developing application software to robustly handle lost messages will minimize application impact. break ? break the bdlc cannot transmit a break symbol. if the bdlc is transmitting at the time a break is detected, it treats the break as if a transmission error had occurred and halts transmission. if the bdlc detects a break symbol while receivi ng a message, it treats the break as a reception error and sets the invalid symbol flag in the bsvr, also ignoring the frame it was receiving. if while receiving a message in 4x mode, the bdlc de tects a break symbol, it treats the break as a reception error, sets the invalid symbol flag, and exits 4x mode (for example, the rx4xe bit in bcr2 is cleared automatically). if bus control is requir ed after the break symbol is received and the ifs time has elapsed, the programmer must resend t he transmission byte using highest priority. note the j1850 protocol break symbol is not related to the hc08 break module. refer to 18.2 break module (brk) . idle ? idle bus an idle condition exists on the bus during any passi ve period after expiration of the ifs period (for instance, 300 s). any node sensing an idle bus conditi on can begin transmission immediately. 4.4.3 j1850 vpw symbols huntsinger?s variable pulse width modulation (vpw) is an encoding technique in which each bit is defined by the time between successive tr ansitions and by the level of the bus between transitions (for instance, active or passive). active and passive bits are used alternately. this encoding technique is used to reduce the number of bus transitions for a given bit rate. each logic 1 or logic 0 contains a si ngle transition and can be at either the active or passive level and one of two lengths, either 64 s or 128 s (t nom at 10.4 kbps baud rate), depending upon the encoding of the previous bit. the start-of-frame (sof), end-of-data (eod), end-of-frame (eof), and inter-frame separation (ifs) symbols always will be encoded at an assigned level and length. see figure 4-7 . each message will begin with an sof symbol an active symbol and, therefore, each data byte (including the crc byte) will begin with a passive bit, regardless of whether it is a 1 or a 0. all vpw bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit rate. logic 0 a logic 0 is defined as either: ? an active-to-passive transition followed by a passive period 64 s in length, or ? a passive-to-active transition followed by an active period 128 s in length see figure 4-7(a) .
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 76 freescale semiconductor figure 4-7. j1850 vpw symbols with nominal symbol times logic 1 a logic 1 is defined as either: a. an active-to-passive transition followed by a passive period 128 s in length, or b. a passive-to-active transition followed by an active period 64 s in length see figure 4-7(b ). normalization bit (nb) the nb symbol has the same property as a logic 1 or a logic 0. it is only used in ifr message responses. break signal (break) the break signal is defined as a pa ssive-to-active transition followed by an active period of at least 240 s. see figure 4-7(c) . start-of-frame symbol (sof) the sof symbol is defined as passive-to-active transition followed by an active period 200 s in length (see figure 4-7(d) ). this allows the data bytes which follow the sof symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. end-of-data symbol (eod) the eod symbol is defined as an active-to-passive transition followed by a passive period 200 s in length (see figure 4-7(e) ). 128 s active passive 64 s or (a) logic 0 128 s active passive 64 s or ( b) logic 1 200 s active passive ( d) start of frame active passive (f) end of frame 240 s (c) break 200 s ( e) end of data 280 s (g) inter-frame 20 s 300 s idle > 300 s (h) idle separation
bdlc mux interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 77 end-of-frame symbol (eof) the eof symbol is defined as an active-to-pa ssive transition followed by a passive period 280 s in length (see figure 4-7 (f) ) . if no ifr byte is transmitted after an eod symbol is transmitted, after another 80 s the eod becomes an eof, indicating completion of the message. inter-frame separation symbol (ifs) the ifs symbol is defined as a passive period 300 s in length. the 20- s ifs symbol contains no transition, since when used it al ways appends to an eof symbol (see figure 4-7(g) ). idle an idle is defined as a passive period greater than 300 s in length. 4.4.4 j1850 vpw valid/inval id bits and symbols the timing tolerances for receiving data bits and symbols from the j1850 bus have been defined to allow for variations in oscillator frequencies. in many case s the maximum time allowed to define a data bit or symbol is equal to the minimum time allo wed to define another data bit or symbol. since the minimum resolution of the bdlc for deter mining what symbol is bei ng received is equal to a single period of the mux interface clock (t bdlc ), an apparent separation in these maximum time/minimum time concurrences equal to one cycle of t bdlc occurs. this one clock resolution allows the bdlc to different iate properly between the different bits and symbols. this is done without reducing the valid window for rece iving bits and symbols fr om transmitters onto the j1850 bus which have varying oscillator frequencies. in huntsinger?s? variable pulse widt h (vpw) modulation bit encoding, the tolerances for both the passive and active data bits received and the symbols receiv ed are defined with no gaps between definitions. for example, the maximum length of a passive logic 0 is equal to the minimum lengt h of a passive logic 1, and the maximum length of an active logic 0 is equal to the minimum length of a valid sof symbol. see figure 4-8 . figure 4-8. j1850 vpw received passive symbol times a bc b a (1) invalid passive bit (2) valid passive logic 0 (3) valid passive logic 1 64 s 128 s cd (4) valid eod symbol 200 s active passive active passive active passive active passive
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 78 freescale semiconductor invalid passive bit see figure 4-8(1) . if the passive-to-active received trans ition beginning the next data bit or symbol occurs between the active-to-passive transiti on beginning the current data bit (or symbol) and a , the current bit would be invalid. valid passive logic 0 see figure 4-8(2) . if the passive-to-active received trans ition beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 0. valid passive logic 1 see figure 4-8(3) . if the passive-to-active received trans ition beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 1. valid eod symbol see figure 4-8(4) . if the passive-to-active received trans ition beginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid end-of-data symbol (eod). valid eof and ifs symbol see figure 4-9 . figure 4-9. j1850 vpw received passive eof and ifs symbol times in figure 4-9(1) , if the passive-to-active received transition beginning the sof symbol of the next message occurs between a and b , the current symbol will be considered a valid end-of-frame (eof) symbol. see figure 4-9(2) . if the passive-to-active received transit ion beginning the sof symbol of the next message occurs between c and d , the current symbol will be consi dered a valid eof symbol followed by a valid inter-frame separation sy mbol (ifs). all nodes must wait until a valid ifs symbol time has expired before beginning transmission. however, d ue to variations in clock frequencies and bus loading, some nodes may recognize a valid if s symbol before others and immediately begin transmitting. therefore, any time a node waiting to transmit detects a passive -to-active transition once a valid eof has been detected, it should immediat ely begin transmission, initiating the arbitration process. idle bus in figure 4-9(2) , if the passive-to-active received transiti on beginning the start-of-frame (sof) symbol of the next message does not occur before d, the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. cd (2) valid eof+ 280 s 300 s a b ( 1) valid eof symbol active passive active passive ifs symbol
bdlc mux interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 79 figure 4-10. j1850 vpw received active symbol times invalid active bit in figure 4-10(1) , if the active-to-passive received transiti on beginning the next data bit (or symbol) occurs between the passive-to-active transiti on beginning the current data bit (or symbol) and a , the current bit would be invalid. valid active logic 1 in figure 4-10(2) , if the active-to-passive received transiti on beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 1. valid active logic 0 in figure 4-10(3) , if the active-to-passive received transiti on beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 0. valid sof symbol in figure 4-10(4) , if the active-to-passive received transiti on beginning the next data bit (or symbol) occurs between c and d , the current symbol would be c onsidered a valid sof symbol. valid break symbol in figure 4-11 , if the next active-to-passive received transition does not occur until after e , the current symbol will be considered a valid break sym bol. a break symbol s hould be followed by a start-of-frame (sof) symbol beginning the next message to be transmitted onto the j1850 bus. see 4.4.2 j1850 frame format for bdlc response to break symbols. a bc b a (1) invalid active bit (2) valid active logic 1 (3) valid active logic 0 64 s 128 s cd (4) valid sof symbol 200 s active passive active passive active passive active passive
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 80 freescale semiconductor figure 4-11. j1850 vpw received break symbol times 4.4.5 message arbitration message arbitration on the j1850 bus is accompli shed in a non-destructive manner, allowing the message with the highest priority to be transmitted, wh ile any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. if the bdlc wants to transmit onto the j1850 bus, but detects that another message is in progress, it waits until the bus is idle. however, if multiple nodes beg in to transmit in the same synchronization window, message arbitration will occur beginning with the first bit after the sof sym bol and will continue with each bit thereafter. the variable pulse width modulation (vpw) symbols and j1850 bus electrical characteristics are chosen carefully so that a logic 0 (active or passive type) wi ll always dominate over a logic 1 (active or passive type) that is simultaneously transmi tted. hence, logic 0s are said to be dominant and logic 1s are said to be recessive. whenever a node detects a dominant bit on bdrxd w hen it transmitted a recessive bit, the node loses arbitration and immediately stops transmitti ng. this is known as bitwise arbitration. since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and will always win arbitrati on. for instance, a message with priority 000 will win arbitration over a message with priority 011. this method of arbitration will work no matter how m any bits of priority encoding are contained in the message. during arbitration, or even throughout the transmi tting message, when an opposite bit is detected, transmission is stopped immediately unless it occurs on the 8th bit of a byte. in this case, the bdlc automatically will append up to two extra logic 1 bits and then stop transmitting. these two extra bits will be arbitrated normally and thus will not interfere wi th another message. the second logic 1 bit will not be sent if the first loses arbitration. if the bdlc has lost arbitration to another valid message, then the two extra logic 1s will not corrupt the current message. howe ver, if the bdlc has lost arbitration due to noise on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored as a noise-corrupted message. (2) valid break symbol 240 s e active passive
bdlc protocol handler mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 81 figure 4-12. j1850 vpw bitwise arbitrations 4.5 bdlc protocol handler the protocol handler is responsib le for framing, arbitration, crc generation/checking, and error detection. the protocol handler conforms to sae j1850 ? class b data communications network interface . note freescale assumes that the reader is familiar with the j1850 specification before this protocol handler description is read. figure 4-13. bdlc block diagram sof data bit 1 data bit 4 data bit 5 0 transmitter a detects an active state on the bus and stops transmitting transmitter b wins 0 0 1 1 1 data bit 2 1 1 1 data bit 3 0 0 0 0 1 arbitration and continues transmitting active transmitter a passive active transmitter b passive active j1850 bus passive cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 82 freescale semiconductor 4.5.1 protocol architecture the protocol handler contains the state machine, rx shadow register, tx shadow register, rx shift register, tx shift register, and loopback multiplexer as shown in figure 4-14 . figure 4-14. bdlc protocol handler outline 4.5.2 rx and tx shift registers the rx shift register gathers received serial data bits from the j1850 bus and makes them available in parallel form to the rx shadow register. the tx shift register takes data, in parallel form, from the tx shadow register and presents it serially to the state machine so that it can be transmitted onto the j1850 bus. 4.5.3 rx and tx shadow registers immediately after the rx shift register has completed shifting in a byte of data, this data is transferred to the rx shadow register and rdrf or rxifr is set (see 4.6.4 bdlc state vector register ) and an interrupt is generated if the interrupt enable bit (ie) in bcr1 is set. after the transfer takes place, this new data byte in the rx shadow register is available to t he cpu interface, and the rx shift register is ready to shift in the next byte of data. data in the rx shadow register must be retrieved by the cpu before it is overwritten by new data from the rx shift register. once the tx shift register has completed its shifting o peration for the current byte, the data byte in the tx shadow register is loaded into the tx shift register. a fter this transfer takes place, the tx shadow register is ready to accept new data from the cpu when tdre flag in bsvr is set. rx shift register to cpu interface and rx/tx buffers state machine to physical interface rx data tx data control 8 tx shift register bdtxd rxd control 8 rx shadow register tx shadow register loopback bdrxd bdtxd multiplexer dloop from bcr2 aloop loopback control
bdlc protocol handler mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 83 4.5.4 digital loopback multiplexer the digital loopback multiplexer connec ts rxd to either bdtxd or bdrxd, depending on the state of the dloop bit in the bcr2 register (see 4.6.3 bdlc control register 2 ). 4.5.5 state machine all of the functions associated with performing t he protocol are executed or controlled by the state machine. the state machine is responsible fo r framing, collision detec tion, arbitration, crc generation/checking, and error detection. the followi ng subsections describe t he bdlc?s actions in a variety of situations. 4.5.5.1 4x mode the bdlc can exist on the same j1850 bus as modul es which use a special 4x (41.6 kbps) mode of j1850 variable pulse width modulation (vpw) operation. the bdlc cannot transmit in 4x mode, but can receive messages in 4x mode, if the rx4x bit is set in bcr2 register. if the rx4x bit is not set in the bcr2 register, any 4x message on the j1850 bus is treated as noise by the bdlc and is ignored. 4.5.5.2 receiving a message in block mode although not a part of the sae j1850 protocol, the bdlc does allow for a specia l block mode of operation of the receiver. as far as the bdlc is concern ed, a block mode message is simply a long j1850 frame that contains an indefinite number of data bytes. all of the other features of the frame remain the same, including the sof, crc, and eod symbols. another node wishing to send a block mode transmissi on must first inform all other nodes on the network that this is about to happen. this is usually ac complished by sending a special predefined message. 4.5.5.3 transmitting a message in block mode a block mode message is transmitted inherently by si mply loading the bytes one by one into the bdr register until the message is complete. the programmer should wait until the tdre flag (see 4.6.4 bdlc state vector register ) is set prior to writing a new byte of data into the bdr register. the bdlc does not contain any predefined maximum j1850 message length requirement. 4.5.5.4 j1850 bus errors the bdlc detects several types of transmit and rece ive errors which can occur during the transmission of a message onto the j1850 bus. transmission error if the message transmitted by the bdlc contains invalid bits or framing symbols on non-byte boundaries, this constitutes a transmission error. when a transmission error is detected, the bdlc immediately will cease transmitting. the error conditi on ($1c) is reflected in the bsvr register (see table 4-5 ). if the interrupt enable bit (ie in bcr1) is set, a cpu interrupt request from the bdlc is generated. crc error a cyclical redundancy check (crc) error is detected when the data bytes and crc byte of a received message are processed and the crc calculation result is not equal to $c4. the crc code will detect any single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. the crc error flag ($18 in bsvr) is set when a crc error is detected. see 4.6.4 bdlc state vector register .
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 84 freescale semiconductor symbol error a symbol error is detected when an abnormal (invalid ) symbol is detected in a message being received from the j1850 bus. however, if the bdlc is transmi tting when this happens, it will be treated as a loss of arbitration ($14 in bsvr) rather than a transmitter error. the ($1c) symbol invalid or the out-of-range flag is set when a symbol error is detect ed. therefore, ($1c) symbol invalid flag is stacked behind the ($14) loa flag during a transmission error process. see 4.6.4 bdlc state vector register . framing error a framing error is detected if an eod or eof symbol is detected on a non-byte boundary from the j1850 bus. a framing error also is detected if the bdlc is transmitting the eod and instead receives an active symbol. the ($1c) sym bol invalid or the out-of-range flag is set when a framing error is detected. see 4.6.4 bdlc state vector register . bus fault if a bus fault occurs, the response of the bdlc will depend upon the type of bus fault. if the bus is shorted to battery, the bdlc will wait for the bus to fall to a passive state before it will attempt to transmit a message. as long as the short remains, the bdlc will never attempt to transmit a message onto the j1850 bus. if the bus is shorted to ground, the bdlc will se e an idle bus, begin to transmit the message, and then detect a transmission error ($1c in bsvr), since t he short to ground would not allow the bus to be driven to the active (dominant) sof state. the bdlc will abort that transmission and wait for the next cpu command to transmit. in any case, if the bus fault is temporary, as soon as the fault is cleared, the bdlc will resume normal operation. if the bus fault is permanent, it may resu lt in permanent loss of communication on the j1850 bus. see 4.6.4 bdlc state vector register . break ? break if a break symbol is received while the bdlc is transmitting or receiving, an invalid symbol ($1c in bsvr) interrupt will be generated. reading the bsvr register (see 4.6.4 bdlc state vector register ) will clear this interrupt condition. the bdlc will wait for the bus to idle, then wait for a start-of-frame (sof) symbol. the bdlc cannot transmit a br eak symbol. it can only receive a br eak symbol from the j1850 bus. 4.5.5.5 summary table 4-1. bdlc j1850 bus error summary error condition bdlc function transmission error for invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt will be generated. bdlc stops transmission. cyclical redundancy check (crc) error crc error interrupt will be generated. the bdlc will wait for sof. invalid symbol: bdlc receives invalid bits (noise) the bdlc will abort transmission immediately. invalid symbol interrupt will be generated. framing error invalid symbol interrupt will be generat ed. the bdlc will wait for start-of-frame (sof). bus short to v dd the bdlc will not transmit until the bus is idle. bus short to gnd thermal overload will shut down physical interface. fault condition is reflected in bsvr as an invalid symbol. bdlc receives break symbol. the bdlc will wait for the next valid sof. invalid symbol interrupt will be generated.
bdlc cpu interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 85 4.6 bdlc cpu interface the cpu interface provides the interface between the cpu and the bdlc and consists of five user registers. bdlc analog and roundtrip delay register (bard) bdlc control register 1 (bcr1) bdlc control register 2 (bcr2) bdlc state vector register (bsvr) bdlc data register (bdr) figure 4-15. bdlc block diagram 4.6.1 bdlc analog and roundtrip delay register this register programs the bdlc to compensate for vari ous delays of different external transceivers. the default delay value is16 s. timing adjustments from 9 s to 24 s in steps of 1 s are available. the bard register can be written only once after each re set, after which they become read-only bits. the register may be read at any time. ate ? analog transceiver enable bit the analog transceiver enable (ate) bit is used to se lect either the on-board or an off-chip analog transceiver. 1 = select on-board analog transceiver 0 = select off-chip analog transceiver address: $003b bit 7654321bit 0 read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset:11000111 r= reserved figure 4-16. bdlc analog and roundtrip delay register (bard) cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 86 freescale semiconductor note this device does not contain an on-board transceiver. this bit should be programmed to a logic 0 for proper operation. rxpol ? receive pin polarity bit the receive pin polarity (rxpol) bit is used to select the polarity of an incoming signal on the receive pin. some external analog transceivers invert the receive signal from the j1850 bus before feeding it back to the digital receive pin. 1 = select normal/true polarity; true non-inverted signal from the j1850 bus; for example, the external transceiver does not invert the receive signal 0 = select inverted polarity, where an external tr ansceiver inverts the receive signal from the j1850 bus b03?b00 ? bard offset bits table 4-2 shows the expected transceiver delay with respect to bard offset values. 4.6.2 bdlc control register 1 this register is used to configure and control the bdlc. table 4-2. bdlc transceiver delay bard offset bits b0[3:0] corresponding expected transceiver?s delays ( s) 0000 9 0001 10 0010 11 0011 12 0100 13 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 address: $003c bit 7654321bit 0 read: imsg clks r1 r0 00 ie wcm write: r r reset:11100000 r= reserved figure 4-17. bdlc control register 1 (bcr1)
bdlc cpu interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 87 imsg ? ignore message bit this bit is used to disable the receiver unt il a new start-of-frame (sof) is detected. 1 = disable receiver. when set, all bdlc interrupt requests will be masked and the status bits will be held in their reset state. if this bit is set while the bdlc is receiving a message, the rest of the incoming message will be ignored. 0 = enable receiver. this bit is cleared automatically by the rec eption of an sof symbol or a break symbol. it will then generate interrupt requests and will allow changes of the status register to occur. however, these interrupts may still be masked by the interrupt enable (ie) bit. clks ? clock bit the nominal bdlc operating frequency (f bdlc ) must always be 1.048576 mhz or 1 mhz for j1850 bus communications to take place. the clks register bit allows the user to select the frequency (1.048576 mhz or 1 mhz) used to adjust symbol timing automatically. 1 = binary frequency (1.048576 mhz) selected for f bdlc 0 = integer frequency (1 mhz) selected for f bdlc r1 and r0 ? rate select bits these bits determine the amount by which the frequency of the mcu cgmxclk signal is divided to form the mux interface clock (f bdlc ) which defines the basic timing resolution of the mux interface. they may be written only once after reset, after which they become read-only bits. the nominal frequency of f bdlc must always be 1.048576 mhz or 1.0 mhz for j1850 bus communications to take place. hence, the value programmed into these bits is dependent on the chosen mcu system clock frequency per table 4-3 . . ie? interrupt enable bit this bit determines whether the bdlc will generate cpu interrupt requests in run mode. it does not affect cpu interrupt requests when exiting the bdlc stop or bdlc wait modes. interrupt requests will be maintained until all of the interrupt request sour ces are cleared by performing the specified actions upon the bdlc?s registers. interrupts that were pending at the time that this bit is cleared may be lost. 1 = enable interrupt requests from bdlc 0 = disable interrupt requests from bdlc if the programmer does not wish to use the interrupt capability of the bdlc, the bdlc state vector register (bsvr) can be polled periodically by the programmer to determine bdlc states. see 4.6.4 bdlc state vector register for a description of the bsvr. table 4-3. bdlc rate selection f xclk frequency r1 r0 division f bdlc 1.049 mhz 0 0 1 1.049 mhz 2.097 mhz 0 1 2 1.049 mhz 4.194 mhz 1 0 4 1.049 mhz 8.389 mhz 1 1 8 1.049 mhz 1.000 mhz 0 0 1 1.00 mhz 2.000 mhz 0 1 2 1.00 mhz 4.000 mhz 1 0 4 1.00 mhz 8.000 mhz 1 1 8 1.00 mhz
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 88 freescale semiconductor wcm ? wait clock mode bit this bit determines the operation of the bdlc during cpu wait mode. see 4.7.2 stop mode and 4.7.1 wait mode for more details on its use. 1 = stop bdlc internal cl ocks during cpu wait mode 0 = run bdlc internal clocks during cpu wait mode 4.6.3 bdlc control register 2 this register controls transmitter operations of the bdlc. it is recommended that bset and bclr instructions be used to manipulate data in this register to ensure that the register?s content does not change inadvertently. aloop ? analog loopback mode bit this bit determines whether the j1850 bus will be dr iven by the analog physical interface?s final drive stage. the programmer can use this bit to reset th e bdlc state machine to a known state after the off-chip analog transceiver is placed in loopback mode. when the user clears aloop, to indicate that the off-chip analog transceiver is no longer in loopback mode, the bdlc waits for an eof symbol before attempting to transmit. 1 = input to the analog physical interface?s final drive stage is looped back to the bdlc receiver. the j1850 bus is not driven. 0 = the j1850 bus will be driven by the bdlc. after the bit is cleared, the bdlc requires the bus to be idle for a minimum of end-of-frame symbol time (t trv4 ) before message reception or a minimum of inter-frame symbol time (t trv6 ) before message transmission. see 19.12.1 bdlc transmitter vpw symbol timings . dloop ? digital loopback mode bit this bit determines the source to which the digital receive input (bdrxd) is connected and can be used to isolate bus f ault conditions (see figure 4-14 ). if a fault condition has been detected on the bus, this control bit allows the programmer to connect the digita l transmit output to the digital receive input. in this configuration, data sent from the transmit buffer will be reflected back into the receive buffer. if no faults exist in the bdlc, the fault is in the phy sical interface block or elsewhere on the j1850 bus. 1 = when set, bdrxd is connected to bdtxd. the bdlc is now in digital loopback mode. 0 = when cleared, bdtxd is not connected to bdrxd. the bdlc is taken out of digital loopback mode and can now drive the j1850 bus normally. rx4xe ? receive 4x enable bit this bit determines if the bdlc operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. this feature is useful for fast download of data into a j1850 node for diagnostic or factory programming of the node. 1 = when set, the bdlc is put in 4x receive-only operation. 0 = when cleared, the bdlc transmits and receives at 10.4 kbps. address: $003d bit 7654321bit 0 read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset:11000000 figure 4-18. bdlc control register 2 (bcr2)
bdlc cpu interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 89 nbfs ? normalization bit format select bit this bit controls the format of the normalization bit (nb) (see figure 4-19 ). sae j1850 strongly encourages using an active long (logic 0) for in-f rame responses containing cyclical redundancy check (crc) and an active short (logic 1) for in-frame responses without crc. 1 = nb that is received or transmitted is a 0 wh en the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 1 when the response part of an in-frame response (ifr) does not end with a crc byte. 0 = nb that is received or transmitted is a 1 wh en the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 0 when the response part of an in-frame response (ifr) does not end with a crc byte. teod ? transmit end of data bit this bit is set by the programmer to indicate the end of a message is being sent by the bdlc. it will append an 8-bit crc after completing transmission of the current byte. this bit also is used to end an in-frame response (ifr). if the transmit shadow regi ster is full when teod is set, the crc byte will be transmitted after the current byte in the tx shift register and the byte in the tx shadow register have been transmitted. (see 4.5.3 rx and tx shadow registers for a description of the transmit shadow register.) once teod is set, the transmit data register empty flag (tdre) in the bdlc state vector register (bsvr) is cleared to allow lo wer priority interrupts to occur. see 4.6.4 bdlc state vector register . 1 = transmit end-of-data (eod) symbol 0 = the teod bit will be cleared automatically at the rising edge of the first crc bit that is sent or if an error is detected. when teod is used to end an ifr transmission, teod is cleared when the bdlc receives back a valid eod symbol or an error condition occurs. tsifr, tmifr1, and tmifr0 ? transmit in-frame response control bits these three bits control the type of in-frame re sponse being sent. the programmer should not set more than one of these control bits to a 1 at any given time. however, if more than one of these three control bits are set to 1, the priority encoding logic will force these register bits to a known value as shown in table 4-4 . for example, if 011 is written to tsifr, tmifr1, and tmifr0, then internally they will be encoded as 010. however, when these bits are read back, they will read 011. the bdlc supports the in-frame response (ifr) f eature of j1850 by setting these bits correctly. the four types of j1850 ifr are shown below. the purpose of the in-frame response modes is to allow multiple nodes to acknowledge receipt of the data by responding with their personal id or physical address in a concatenated manner after they have se en the eod symbol. if transmission arbitration is lost by a node while sending its response, it continues to transmit its id/address until observing its unique byte in the response stream. for vpw modulation, because the first bit of the ifr is always table 4-4. bdlc transmit in-frame response control bit priority encoding write/read tsifr write/read tmifr1 write/read tmifr0 actual tsifr actual tmifr1 actual tmifr0 000000 1xx100 01x010 001001
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 90 freescale semiconductor passive, a normalization bit (active) must be gener ated by the responder and sent prior to its id/address byte. when there are multiple responder s on the j1850 bus, only one normalization bit is sent which assists all other transmi tting nodes to sync up their response. tsifr ? transmit single byte ifr with no crc (type 1 or 2) bit the tsifr bit is used to request the bdlc to transmit the byte in the bdlc data register (bdr, $003f) as a single byte ifr with no crc. typically, the by te transmitted is a unique identifier or address of the transmitting (responding) node. see figure 4-19 . 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transm it the appropriate normalization bit followed by the byte in the bdr. 0 = the tsifr bit will be cleared automatically, once the bdlc has successfully transmitted the byte in the bdr onto the bus, or teod is set, or an error is detected on the bus. figure 4-19. types of in-frame response (ifr) if the programmer attempts to set the tsifr bit immediately after the eod symbol has been received from the bus, the tsifr bit will remain in the reset state and no attempt will be made to transmit the ifr byte. if a loss of arbitration occurs when the bdlc attempts to transmit and after the ifr byte winning arbitration completes transmission, the bdlc wi ll again attempt to transmit the bdr (with no normalization bit). the bdlc will c ontinue transmission attempts until an error is detected on the bus, or teod is set, or the bdlc transmission is successful. if loss or arbitration occurs in the last tw o bits of the ifr byte, two additional 1 bits will not be sent out because the bdlc will attempt to retr ansmit the byte in the transmit shift register after the irf byte winning arbitration completes transmission. sof header data field crc eod type 0 ? no ifr header data field crc eod type 3 ? multiple bytes transmitted from a single responder header data field crc eod type 1 ? single byte transmitted from a single responder header data field crc eod type 2 ? single byte transmitted from multiple responders id1 id n ifr data field crc nb nb nb id sof sof sof eof eod eof eod eof eod eof (optional) nb = normalization bit id = identifier (usually the phy sical address of the responder(s)) header = specifies one of three frame lengths
bdlc cpu interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 91 tmifr1 ? transmit multiple byte ifr with crc (type 3) bit the tmifr1 bit requests the bdlc to transmit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr with crc or as a sing le byte ifr with crc. response ifr bytes are still subject to j1850 message length maximums. see 4.4.2 j1850 frame format and figure 4-19 . if this bit is set prior to a valid eod being received with no crc e rror, once the eod symbol has been received the bdlc will attempt to transmit the appr opriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr by te has been written into the bdr register. after teod has been set and the last ifr byte has been transmitted, the crc byte is transmitted. the tmifr1 bit will be cleared automatically ? once the bdlc has successfully transmitted the crc byte and eod symbol ? by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr1 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 4.6.4 bdlc state vector register ) will occur similar to the main message transmit sequence. the programmer should then load the next byte of t he ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bdlc control register 2 (bcr2). this will instruct the bdlc to transmit a crc byte once the byte in the bdr is transmitted and then transmit an eod symbol, indi cating the end of the ifr portion of the message frame. however, if the programmer wishes to transmit a si ngle byte followed by a crc byte, the programmer should load the byte into the bdr before the eod symbol has been received, and then set the tmifr1 bit. once the tdre interrupt occurs, the programmer should then set the teod bit in the bcr2. this will result in the byte in the bdr being the only byte transmitted before the ifr crc byte, and no tdre interrupt will be generated. if the programmer attempts to set the tmifr1 bit immediately after the eod symbol has been received from the bus, the tmifr1 bit will remain in the rese t state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is trans mitting any byte of a multiple byte ifr, the bdlc will go to the loss of arbitration state, set the appropriate flag, and cease transmission. if the bdlc loses arbitration during the ifr, the tmifr1 bit will be cleared and no attempt will be made to retransmit the byte in the bdr. if loss of arbitrat ion occurs in the last two bits of the ifr byte, two additional 1 bits will be sent out. note the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. tmifr0 ? transmit multiple byte ifr without crc (type 3) bit the tmifr0 bit is used to request the bdlc to trans mit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr without crc. response ifr bytes are still subject to j1850 message length maximums. see 4.4.2 j1850 frame format and figure 4-19 . 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transm it the appropriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr register. after teod has been set, the last ifr byte to be transmitted will be the last byte which was written into the bdr register.
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 92 freescale semiconductor 0 = the tmifr0 bit will be cleared automatically ; once the bdlc has succ essfully transmitted the eod symbol; by the detection of an error on the multiplex bus; or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr0 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 4.6.4 bdlc state vector register ) will occur similar to the main message transmit sequence. the programmer should then load the next byte of t he ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bcr2. this will instruct the bdlc to transmit an eod symbol once the byte in the bdr is transmitted, indicating the end of the ifr portion of the message frame. the bdlc will not append a crc when the tmifr0 is set. if the programmer attempts to set the tmifr0 bit after the eod symbol has been received from the bus, the tmifr0 bit will remain in the reset state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is transmitting, the tmifr0 bit will be cleared and no attempt will be made to retransmit the byte in the bdr. if loss of arbitrat ion occurs in the last two bits of the ifr byte, two additional 1 bits (active short bits) will be sent out. note the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. 4.6.4 bdlc state vector register this register is provided to substantially decreas e the cpu overhead associated with servicing interrupts while under operation of a multiplex protocol. it provides an index offset that is directly related to the bdlc?s current state, which can be used with a us er-supplied jump table to rapidly enter an interrupt service routine. this eliminates the need for the us er to maintain a duplicate state machine in software. i0, i1, i2, and i3 ? interrupt source bits these bits indicate the source of the interrupt requ est that currently is pending. the encoding of these bits are listed in table 4-5 . bits i0, i1, i2, and i3 are cleared by a read of the bsvr except when the bdlc data register needs servicing (rdrf, rxifr, or tdre conditions). rx ifr and rdrf can be cleared only by a read of the bsvr followed by a read of the bdlc data register (bdr). tdre can either be cleared by a read of the bsvr followed by a write to the bdlc bdr or by setting the teod bit in bcr2. address: $003e bit 7654321bit 0 read:0 0 i3i2i1i0 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 4-20. bdlc state vector register (bsvr)
bdlc cpu interface mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 93 upon receiving a bdlc interrupt, the user can read the value within the bsvr, transferring it to the cpu?s index register. the value can then be used to index into a jump table, with entries four bytes apart, to quickly enter the appropriate service routine. for example: note the nops are used only to align t he jmps onto 4-byte boundaries so that the value in the bsvr can be used intact. each of the service routines must end with an rti instruction to guarantee correct continued operation of the device. note also that the first entry can be omitted since it corresponds to no interrupt occurring. the service routines should clear all of the sources t hat are causing the pending interrupts. note that the clearing of a high priority interrupt may still leave a lo wer priority interrupt pending, in which case bits i0, i1, and i2 of the bsvr will then reflect the source of the remaining interrupt request. if fewer states are used or if a different software app roach is taken, the jump table can be made smaller or omitted altogether. table 4-5. bdlc interrupt sources bsvr i3 i2 i1 i0 interrupt source priority $00 0000 no interrupts pending 0 (lowest) $04 0001 received eof 1 $08 0010 received ifr byte (rxifr) 2 $0c 0011 bdlc rx data register full ( rdrf) 3 $10 0100 bdlc tx data register empty (tdre) 4 $14 0101 loss of arbitration 5 $18 0110 cyclical r edundancy check (crc) error 6 $1c 0111 symbol invalid or out of range 7 $20 1000 wakeup 8 (highest) service ldx bsvr fetch state vector number jmp jmptab,x enter service routine, * (must end in rti) * jmptab jmp serve0 service condition #0 nop jmp serve1 service condition #1 nop jmp serve2 service condition #2 nop * jmp serve8 service condition #8 end
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 94 freescale semiconductor 4.6.5 bdlc data register this register is used to pass the data to be transmitted to the j1850 bus from the cpu to the bdlc. it is also used to pass data received from the j1850 bus to the cpu. each data byte (after the first one) should be written only after a tx data register empty (tdre) state is indicated in the bsvr. data read from this register will be the last data byte received from the j1850 bus. this received data should only be read after an rx data register full (rdrf) interrupt has occurred. see 4.6.4 bdlc state vector register . the bdr is double buffered via a transmit shadow regi ster and a receive shadow register. after the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. once the trans mit shift register has shifted the first bit out, the tdre flag is set, and the shadow register is ready to accept the next data byte. the receive shadow register works similarly. once a complete byte has been received, the receive shift register stores the newly received byte into the receive shadow register. the rdrf flag is set to indicate that a new byte of data has been received. the programmer has one bdlc byte reception time to read the shadow register and clear the rdrf flag before the shadow regist er is overwritten by the newly received byte. to abort an in-progress transmission, the programmer should stop loading data into the bdr. this will cause a transmitter underrun error and the bdlc automat ically will disable the transmitter on the next non-byte boundary. this means that the earliest a tr ansmission can be halted is after at least one byte plus two extra logic 1s have been transmitted. the receiver will pick this up as an error and relay it in the state vector register as an invalid symbol error. note the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. 4.7 low-power modes the following information concerns wait mode and stop mode. 4.7.1 wait mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a wait instruction and the wcm bit in bdlc control register 1 (bcr1) is previously clear. in bdlc wait mode, the bdlc cannot drive any data. a subsequent successfully received message, including one that is in progress at the time that this mode is entered, will cause the bdlc to wake up and generate a cpu interrupt request if the interrupt enable (ie) bit in the bdlc control register 1 (bcr1) is previously set. (see 4.6.2 bdlc control register 1 for a address: $003f bit 7654321bit 0 read: d7 d6 d5 d4 d3 d2 d1 d0 write: reset: unaffected by reset figure 4-21. bdlc data register (bdr)
low-power modes mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 95 better understanding of ie.) this results in less of a power saving, but the bdlc is guaranteed to receive correctly the message which woke it up, since the bdlc internal operating clocks are kept running. note ensuring that all transmissions are complete or aborted before putting the bdlc into wait mode is important. 4.7.2 stop mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait instruction and the wcm bit in the bdlc control register 1 (bcr1) is previously set. this is the lowest power mode that the bdlc can enter. a subsequent passive-to-active transition on the j18 50 bus will cause the bdlc to wake up and generate a non-maskable cpu interrupt request. when a stop inst ruction is used to put the bdlc in stop mode, the bdlc is not guaranteed to correctly receive the message which woke it up, since it may take some time for the bdlc internal operating clocks to restart and stabilize. if a wait instruction is used to put the bdlc in stop mode, the bdlc is guaranteed to correctly receive the byte which woke it up, if and only if an end-of-frame (eof) has been detected prior to issuing the wait instruction by the cpu. otherwise, the bdlc will not correctly rece ive the byte that woke it up. if this mode is entered while the bdlc is receivi ng a message, the first subsequent received edge will cause the bdlc to wake up immediately, generat e a cpu interrupt request, and wait for the bdlc internal operating clocks to restart and stabilize before normal communications can resume. therefore, the bdlc is not guaranteed to receive that message correctly. note it is important to ensure all transmissions are complete or aborted prior to putting the bdlc into stop mode.
byte data link controller (bdlc) mc68hc908as32a data sheet, rev. 2.0 96 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 97 chapter 5 clock generator module (cgm) 5.1 introduction the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmo ut, from which the system clocks are derived. cgmout is based on either the crystal clock divide d by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequenc y generator designed for use with 1-mhz to 8-mhz crystals or ceramic resonators. the pll can generate an 8-mhz bus frequency without using high frequency crystals. 5.2 features features include: phase-locked loop with output frequency in in teger multiples of the crystal reference programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 5.3 functional description the cgm consists of three major submodules: crystal oscillator circuit ? the crystal oscillat or circuit generates the constant crystal frequency clock, cgmxclk. phase-locked loop (pll) ? the pll generates the programmable vco frequency clock cgmvclk. base clock selector circuit ? this software-cont rolled circuit selects either cgmxclk divided by two or the vco clock, cgmvclk, divided by two as the base clock, cgmout. the system clocks are derived from cgmout. figure 5-2 shows the structure of the cgm.
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 98 freescale semiconductor figure 5-1. block diagram highlighting cgm block and pins break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 99 figure 5-2. cgm block diagram 5.3.1 crystal os cillator circuit the crystal oscillator circuit consists of an inverting am plifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the out put. the simoscen signal enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to pr oduce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on ex ternal factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal osci llator circuit. connect the external clock to the osc1 pin and let the osc2 pin float. phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmvdv cgmvclk interrupt control cgmint cgmrdv pll analog cgmrclk select circuit lock auto acq vrs7?vrs4 pllie pllf mul7?mul4 v dda cgmxfc v ss osc1 cgmxclk ptc3 monitor mode bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 100 freescale semiconductor 5.3.2 phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. 5.3.2.1 circuits the pll consists of these circuits: voltage-controlled oscillator (vco) modulo vco frequency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, incl uding supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f cgmvrs . modulating the voltage on the cgmxfc pin changes the frequency wi thin this range. by design, f cgmvrs is equal to the nominal center-of-range frequency, f nom , (4.9152 mhz) times a linear factor l or (l)f nom . cgmrclk is the pll reference clock, a buffered ve rsion of cgmxclk. cgmrclk runs at a frequency, f cgmrclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency f cgmrdv =f cgmrclk . the vco?s output clock, cgmvclk, running at a frequency f cgmvclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco clock by a factor, n. the divider?s output is the vco feedback clock, cgmvdv, running at a frequency f cgmvdv =f cgmvclk /n. see 5.3.2.4 programming the pll for more information. the phase detector then compares the vco feedback cloc k, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor c onnected to cgmxfc based on the width and direction of the correction pulse. the fi lter can make fast or slow corrections depending on its mode, as described in 5.3.2.2 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency, f cgmrdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 5.3.2.2 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: acquisition mode ? in acquisition mode, the filt er can make large frequency corrections to the vco. this mode is used at pll startup or when the pll has suffered a severe noise hit and the vco frequency is far off the desired freq uency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. see 5.5.2 pll bandwidth control register for more information.
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 101 tracking mode ? in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. see 5.3.3 base clock selector circuit for more information. the pll is automatically in tracking mode when it?s not in acquisition mode or when the acq bit is set. 5.3.2.3 manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manua lly or automatically. in automatic bandwidth control mode (auto = 1), th e lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is used to determine when the vco clock, cgmvclk, is safe to use as th e source for the base clock, cgmout. see 5.5.2 pll bandwidth control register for more information. if pll cpu interrupt requests are enabled, the software can wait for a pll cpu interrupt request and then c heck the lock bit. if cpu interrupts are disabled, software can poll the lock bit continuously (during pll st artup, usually) or at periodic intervals. in either case, when the lock bit is set, the vco clock is sa fe to use as the source for the base clock. see 5.3.3 base clock selector circuit for more information. if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. see 5.6 interrupts for more information. these conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 5.5.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. see 5.3.2.2 acquisition and tracking modes for more information. the acq bit is set when the vco frequency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . see chapter 19 electrical specifications for more information. the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco freq uency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . see chapter 19 electrical specifications for more information. cpu interrupts can occur if enabled (pllie = 1) when the pll?s lock c ondition changes, toggling the lock bit. see 5.5.1 pll control register for more information. the pll also can operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast startup. the followi ng conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see chapter 19 electrical specifications for more information), after turning on the pll by setting pllon in the pll control register (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled.
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 102 freescale semiconductor 5.3.2.4 programming the pll use this 9-step procedure to program the pll. table 5-1 lists the variables used and their meaning. please also reference figure 5-2 . 1. choose the desired bus frequency, f busdes . example: f busdes = 8 mhz 2. calculate the desired vco frequency, f vclkdes . f vclkdes = 4 f busdes example: f vclkdes = 4 8 mhz = 32 mhz 3. using a reference frequency, f rclk , equal to the crystal frequency, calculate the vco frequency multiplier, n. round the result to the nearest integer. example: 4. calculate the vco frequency, f cgmvclk . example: f cgmvclk = 8 4 mhz = 32 mhz 5. calculate the bus frequency, f bus , and compare f bus with f busdes . example: 6. if the calculated f bus is not within the tolerance limits of your application, select another f busdes or another f rclk . table 5-1. variable definitions variable definition f busdes desired bus clock frequency f vclkdes desired vco clock frequency f cgmrclk chosen reference crystal frequency f cgmvclk calculated vco clock frequency f bus calculated bus clock frequency f nom nominal vco center frequency f cgmvrs shifted vco center frequency n f vclkdes f cgmrclk --------------------------- - = n 32 mhz 4 mhz -------------------- =8 = f cgmvclk nf cgmrclk = f bus f cgmvclk 4 ------------------------------- = f bus 32 mhz 4 -------------------- =8 mhz =
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 103 7. using the value 4.9152 mhz for f nom , calculate the vco linear range multiplier, l. the linear range multiplier controls the frequency range of the pll. example: 8. calculate the vco center-of-range frequency, f cgmvrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. f cgmvrs = l f nom example: f cgmvrs = 7 4.9152 mhz = 34.4 mhz note for proper operation, exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. 9. program the pll registers accordingly: a. in the upper four bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower four bits of the pll programming register (ppg), program the binary equivalent of l. 5.3.2.5 special programming exceptions the programming method described in 5.3.2.4 programming the pll , does not account for two possible exceptions. a value of 0 for n or l is meaningless when used in the equations given. to account for these exceptions: a 0 value for n is interpreted the same as a value of 1. a 0 value for l disables the pll and prevents its selection as the source for the base clock. see 5.3.3 base clock selector circuit for more information. 5.3.3 base clock se lector circuit this circuit is used to select either the crystal cl ock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input cl ocks go through a transition c ontrol circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the outpu t of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus cl ock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the l round f cgmvclk f nom ------------------------- - ?? ?? ?? = l 32 mhz 4.9152 mhz ------------------------------- - =7 = f cgmvrs f cgmvclk ? f nom 2 ------------ -
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 104 freescale semiconductor factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crysta l clock would be forced as the source of the base clock. 5.3.4 cgm exte rnal connections in its typical configuration, the cgm requires seven ex ternal components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 5-3 . figure 5-3 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) may not be required for all ranges of o peration, especially with high-frequency crystals. refer to the crystal manufacturer?s data for more information. figure 5-3 also shows the external components for the pll: bypass capacitor, c byp filter capacitor, c f routing should be done with great care to minimize signal cross talk and noise. (see 5.9 acquisition/lock time specifications for routing information and more informat ion on the filter capacitor?s value and its effects on pll performance). figure 5-3. cgm external connections c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp *r s can be 0 (shorted) when used with higher-frequency crystals. refer to manufacturer?s data. osc1 osc2 v ss cgmxfc v dd v dda
i/o signals mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 105 5.4 i/o signals the following paragraphs describe the cgm input/output (i/o) signals. 5.4.1 crystal amplifi er input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 5.4.2 crystal amplifi er output pin (osc2) the osc2 pin is the output of the cr ystal oscillator inverting amplifier. 5.4.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filt er out phase corrections. a sm all external capacitor is connected to this pin. note to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible with minimum routing distances and no routing of other signals across the c f connection. 5.4.4 analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same voltage potential as the v dd pin. note route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 5.4.5 oscillator e nable signal (simoscen) the simoscen signal enables the oscillator and pll. 5.4.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f cgmxclk ) and comes directly from the crystal oscillator circuit. figure 5-3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at startup. 5.4.7 cgm base cl ock output (cgmout) cgmout is the clock output of the cgm. this signa l is used to generate the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. 5.4.8 cgm cpu interrupt (cgmint) cgmint is the cpu interrupt signal generated by the pll lock detector.
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 106 freescale semiconductor 5.5 cgm registers three registers control and monitor operation of the cgm: pll control register (pctl) pll bandwidth control register (pbwc) pll programming register (ppg) 5.5.1 pll control register the pll control register (pctl) contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate a cpu interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as a 0. reset clears the pllie bit. 1 = pll cpu interrupt requests enabled 0 = pll cpu interrupt requests disabled pllf ? pll flag bit this read-only bit is set whenever the lock bit toggles. pllf generates a cpu interrupt request if the pllie bit also is set. pllf always reads as 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note do not inadvertently clear the pllf bit. be aware that any read or read-modify-write operation on the pll control register clears the pllf bit. pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving th e base clock, cgmout (bcs = 1). see 5.3.3 base clock selector circuit for more information. reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output , cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, address: $001c bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: reset:00101111 = unimplemented figure 5-4. pll control register (pctl)
cgm registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 107 it may take up to three cgmxclk and three cgmv clk cycles to complete the transition from one source clock to the other. during the trans ition, cgmout is held in stasis. see 5.3.3 base clock selector circuit for more information. reset and the stop instruction clear the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note pllon and bcs have built-in protecti on that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is cl ear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. see 5.3.3 base clock selector circuit for more information. pctl3?pctl0 ? unimplemented these bits provide no func tion and always read as 1s. 5.5.2 pll bandwidth control register the pll bandwidth control register: selects automatic or manual (softw are-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates wh en the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode auto ? automatic bandwidth control bit this read/write bit selects automatic or manual b andwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). wh en the auto bit is clear, lock reads as 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. address: $001d bit 7654321bit 0 read: auto lock acq xld 0000 write: reset:00000000 = unimplemented figure 5-5. pll bandwidth control register (pbwc)
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 108 freescale semiconductor in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ? crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit ca n indicate whether the crystal reference frequency is active or not. 1 = crystal reference not active 0 = crystal reference active to check the status of the crystal reference, do the following: 1. write a 1 to xld. 2. wait n 4 cycles. n is the vco frequency multiplier. 3. read xld. the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as 0. bits 3?0 ? reserved for test these bits enable test functions not available in us er mode. to ensure software portability from development systems to user applications, software sh ould write 0s to bits 3?0 when writing to pbwc. 5.5.3 pll programming register the pll programming register contains the progra mming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul7?mul4 ? multiplier select bits these read/write bits control the modulo feedback di vider that selects the vco frequency multiplier, n. (see 5.3.2.1 circuits and 5.3.2.4 programming the pll ). a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a va lue of $1. reset initializes these bits to $6 to give a default multiply value of 6. address: $001e bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 5-6. pll programming register (ppg) table 5-2. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco fr equency multiplier (n) 0000 1 0001 1 0010 2 0011 3
interrupts mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 109 note the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). vrs7?vrs4 ? vco range select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware center-of-range frequency, f vrs . (see 5.3.2.1 circuits , 5.3.2.4 programming the pll , and 5.5.1 pll control register for more information.) vrs7?vrs4 cannot be written when the pllon bit in the pll control register (pctl) is set. see 5.3.2.5 special programming exceptions for more information. a value of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. (see 5.3.3 base clock selector circuit and 5.3.2.5 special programming exceptions for more information.) reset initializes the bits to $6 to give a default range multiply value of 6. note the vco range select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming can result in failure of the pll to achieve lock. 5.6 interrupts when the auto bit is set in the pll bandwidth c ontrol register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupt requests from the pll. pllf, the interrupt flag in the pctl, becomes set whether cpu interrupt requests are enabled or not. when the auto bit is clear, cpu interrupt requests from the pll are disabled and pllf reads as 0. software should read the lock bit after a pll cpu interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precaution s should be taken. if the application is not frequency sensitive, cpu interrupt requests should be disabled to prevent pll interrupt service routines from impeding software performance or fr om exceeding stack limitations. note software can select the cgmvclk divi ded by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 1101 13 1110 14 1111 15 table 5-2. vco frequency multiplier (n) selection (continued) mul7:mul6:mul5:mul4 vco fr equency multiplier (n)
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 110 freescale semiconductor 5.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 5.7.1 wait mode the cgm remains active in wait mode. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. 5.7.2 stop mode the stop instruction disables the cgm and ho lds low all cgm outputs (cgmxclk, cgmout, and cgmint). if cgmout is being driven by cgmvclk and a stop in struction is executed; the pll will clear the bcs bit in the pll control register, causing cgmout to be driven by cgmxclk. when the mcu recovers from stop, the crystal clock divided by tw o drives cgmout and bcs remains clear. 5.8 cgm during break interrupts the bcfe bit in the break flag control register (bfc r) enables software to clear status bits during the break state. see 18.2 break module (brk) for more information. to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. 5.9 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensure s the highest stability and lowest acquisition/lock times. 5.9.1 acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually sp ecified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. fifty khz = 5% of the 1-mhz step input. if the system is operating at 1 mhz and suffers a ?100 khz noise hit, the acquisition time is the time tak en to return from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to acquisition and lock times as t he time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock
acquisition/lock ti me specifications mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 111 time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition beca use the system requires the output frequency to be within a certain tolerance of the desired frequenc y regardless of the size of the initial error. the discrepancy in these definitions makes it difficul t to specify an acquisition or lock time for a typical pll. therefore, the definitions for acquisition and lock times for this module are: acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ? trk . acquisition time is based on an initial frequency error, (f des ?f orig )/f des , of not more than 100%. in automatic bandwidth control mode (see 5.3.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, ? lock . lock time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes set in the pll bandwidth control register (pbwc). see 5.3.2.3 manual and automatic pll bandwidth modes for more information. obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 5.9.2 parametric in fluences on reaction time acquisition and lock times are designed to be as short as possible while still pr oviding the highest possible stability. these reaction times are not constant, however . many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reac tion times of the pll is the reference frequency, f cgmrdv (please reference figure 5-2 ). this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the co rrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of crystal frequency f cgmxclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus a change in charge) is proportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. see 5.9.3 choosing a filter capacitor for more information. also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. va riable supplies, such as batteries, are acceptable if they vary within a known range at very slow sp eeds. noise on the power s upply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as spec ified as long as thes e influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 112 freescale semiconductor noise injected into the pll through the filter capacito r, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 5.9.3 choosing a filter capacitor as described in 5.9.2 parametric influences on reaction time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. t he pll is also dependent on reference frequency and supply voltage. the value of the capacitor must, theref ore, be chosen with supply potential and reference frequency in mind. for proper operation, the external filter capacitor must be chosen according to this equation: for acceptable values of c fact , (refer to 19.1 introduction ). for the value of v dda , choose the voltage potential at which the mcu is operating. if the pow er supply is variable, c hoose a value near the middle of the range of possible supply values. this equation does not always yield a commonly av ailable capacitor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing the lower size may seem attractive for acquisition time improvement, but the pll may become unstable. also, always choose a ca pacitor with a tight tolerance ( 20% or better) and low dissipation. 5.9.4 reaction ti me calculation the actual acquisition and lock times can be calculated using the equations below. these equations yield nominal values under the following conditions: correct selection of filter capacitor, c f (see 5.9.3 choosing a filter capacitor for more information). room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. see 5.3.2.2 acquisition and tracking modes for more information. note the inverse proportionality between the lock time and the reference frequency. c f c fact a v dda f cgmrdv ------------------------ - ?? ?? ?? = t acq v dda f cgmrdv ------------------------ - ?? ?? ?? 8 k acq -------------- - ?? ?? = t al v dda f cgmrdv ------------------------ - ?? ?? ?? 4 k trk -------------- ?? ?? = t lock t acq t al + =
acquisition/lock ti me specifications mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 113 in automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (refer to 5.3.2.3 manual and automatic pll bandwidth modes .) a certain number of clock cycles, n acq , is required to ascertain that the pll is within the tracking mode entry tolerance, ? trk , before exiting acquisition mode. a certain number of clock cycles, n trk , is required to ascertain that the pll is within the lock mode entry tolerance, ? lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f cgmrdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f cgmrdv . also, since the average frequency over the entire me asurement period must be within the specified tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (refer to 5.3.3 base clock selector circuit ), because the factors described in 5.9.2 parametric influences on reaction time , may slow the lock time considerably. when defining a limit in software for the maximum lock time, the value must allow for variation due to all of the factors mentioned in this section, especially due to the c f capacitor and application specific influences. the calculated lock time is only an indication and it is the customer?s responsibility to allow enough of a guard band for their application. prior to finalizing any software and while determining the maximum lock time, take into account all device to device differe nces. typically, applications set the maximum lock time as an order of magnitude higher than the measured value. this is considered sufficient for all such device to device variation. freescale recommends measuring the lo ck time of the application syste m by utilizing dedicated software, running in flash, eeprom, or ram. this should togg le a port pin when the pll is first configured and switched on, then again when it goes from acquisition to lock mode and finally again when the pll lock bit is set. the resultant waveform can be captur ed on an oscilloscope and used to determine the typical lock time for the microcontroller and the associated external application circuit. for example: note the filter capacitor should be fully discharged prior to making any measurements. t acq t al t lock signal on port pin t trk complete and lock set t acq complete pll configured and switched on init. low
clock generator module (cgm) mc68hc908as32a data sheet, rev. 2.0 114 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 115 chapter 6 configuration register (config1) 6.1 introduction this section describes the configuration register (c onfig1), which contains bits that configure these options: resets caused by the low-voltage inhibit (lvi) module power to the lvi module lvi enabled during stop mode stop mode recovery time (32 cgmx clk cycles or 4096 cgmxclk cycles) computer operating properly (cop) module stop instruction enable/disable 6.2 functional description the configuration register is a write-once register. ou t of reset, the configuration register will read the default value. once the register is written, furt her writes will have no effect until a reset occurs. note if the lvi module and the lvi reset si gnal are enabled, a reset occurs when v dd falls to a voltage, lvi tripf . once an lvi reset occurs, the mcu remains in reset until v dd rises to a voltage, lvi tripr . lvistop ? lvi stop mode enable bit lvistop enables the lvi module in stop mode. refer to chapter 11 low-voltage inhibit (lvi) . 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode note to have the lvi enabled in stop mode, the lvipwr must be at a 1 and the lvistop bit must be at a 1. take note that by enabling the lvi in stop mode, the stop i dd current will be higher. address: $001f bit 7654321bit 0 read: lvistop r lvirst lvipwr ssrec copl stop copd write: reset:01110000 r=reserved figure 6-1. configuration register (config1)
configuration register (config1) mc68hc908as32a data sheet, rev. 2.0 116 freescale semiconductor lvirst ? lvi reset enable bit lvirst enables the reset signal from the lvi module. refer to chapter 11 low-voltage inhibit (lvi) . 1 = lvi module resets enabled 0 = lvi module resets disabled lvipwr ? lvi power enable bit lvipwr enables the lvi module. refer to chapter 11 low-voltage inhibit (lvi) . 1 = lvi module power enabled 0 = lvi module power disabled ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. refer to chapter 15 system integration module (sim) . 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note if using an external crystal oscillator, do not set the ssrec bit. copl ? cop long timeout copl enables the shorter cop timeout period. refer to chapter 8 computer operating properly (cop) . 1 = cop timeout period is 8176 cgmxclk cycles 0 = cop timeout period is 262,128 cgmxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. refer to chapter 8 computer operating properly (cop) . 1 = cop module disabled 0 = cop module enabled
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 117 chapter 7 configuration register (config2) 7.1 introduction this section describes the configurat ion register (config2). this register contains bits that configures the device to either the mc68hc08azxx em ulator or the mc68hc08asxx emulator 7.2 functional description the configuration register is a write-once register. ou t of reset, the configuration register will read the default. once the register is written, further writes will have no effect until a reset occurs. eedivclk ? eeprom timebase di vider clock select bit this bit selects the reference clock sour ce for the eeprom timebase divider module. 1 = eexdiv clock input is driven by internal bus clock 0 = eexdiv clock input is driven by cgmxclk as32a? device indicator bit this bit is used to distinguish mc68hc908 as32a from older non-a suffix versions. 1 = a version 0 = non-a version address: $fe09 bit 7654321bit 0 read: eedivclkrrras32arrr write: reset:00011000 r=reserved figure 7-1. configuration register (config2)
configuration register (config2) mc68hc908as32a data sheet, rev. 2.0 118 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 119 chapter 8 computer operating properly (cop) 8.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop m odule can be disabled through the copd bit in the configuration 1 (config1) register. figure 8-1. cop block diagram copctl write busclkx4 reset vector fetch sim reset circuit reset status register internal reset sources (1) sim module clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) 1. see chapter 15 system integration module (sim) for more details. cop clock cop timeout cop rate select (coprs from config1) 6-bit cop counter cop counter
computer operating properly (cop) mc68hc908as32a data sheet, rev. 2.0 120 freescale semiconductor 8.2 functional description the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler. if not cleared by software, the cop counter overflows and generates an asyn chronous reset after 8176 or 262,128 cgmxclk cycles, depending on the state of the cop long tim eout bit, copl, in the config1. when copl = 0, a 4.9152-mhz crystal gives a cop timeout period of 53.3 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clear ing the cop counter and stages 4 through 12 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the reset status register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq pin is held at v tst . during the break state, v tst on the rst pin disables the cop. note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 8.3 i/o signals the following paragraphs describe the signals shown in figure 8-1 . 8.3.1 cgmxclk cgmxclk is the crystal oscillator output signal. cg mxclk frequency is equal to the crystal frequency. 8.3.2 stop instruction the stop instruction clears the cop prescaler. 8.3.3 copctl write writing any value to the cop control register (c opctl) clears the cop counter and clears stages 12 through 4 of the cop prescaler (refer to 8.4 cop control register ). reading the cop control register returns the reset vector. 8.3.4 powe r-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. 8.3.5 internal reset an internal reset clears the cop prescaler and the cop counter.
cop control register mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 121 8.3.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 8.3.7 copd the copd signal reflects the state of the cop dis able bit (copd) in the configuration register. see chapter 6 configuration register (config1) for more information. 8.3.8 copl the copl signal reflects the state of the cop rate select bit. (copl) in the configuration register. see chapter 6 configuration register (config1) for more information. 8.4 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 8.5 interrupts the cop does not generate cpu interrupt requests. 8.6 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin or on the rst pin. 8.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 8.7.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. 8.7.2 stop mode stop mode turns off the cgmxclk input to the co p and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 8-2. cop control register (copctl)
computer operating properly (cop) mc68hc908as32a data sheet, rev. 2.0 122 freescale semiconductor the stop bit in the configuration register (con fig1) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instru ction, disable the stop instruction by clearing the stop bit. 8.8 cop module during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin.
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 123 chapter 9 central processor unit (cpu) 9.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 9.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 9.3 cpu registers figure 9-1 shows the five cpu registers. cpu registers are not part of the memory map.
central processor unit (cpu) mc68hc908as32a data sheet, rev. 2.0 124 freescale semiconductor figure 9-1. cpu registers 9.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 9.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 9-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 9-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70
cpu registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 125 9.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 9.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 9-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 9-5. program counter (pc)
central processor unit (cpu) mc68hc908as32a data sheet, rev. 2.0 126 freescale semiconductor 9.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 9-6. condition code register (ccr)
arithmetic/logic unit (alu) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 127 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 9.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 9.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 9.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 9.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 9.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted.
central processor unit (cpu) mc68hc908as32a data sheet, rev. 2.0 128 freescale semiconductor 9.7 instruction set summary table 9-1 provides a summary of the m68hc08 instruction set. table 9-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c
instruction set summary mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 129 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 9-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) mc68hc908as32a data sheet, rev. 2.0 130 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 9-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
instruction set summary mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 131 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 9-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) mc68hc908as32a data sheet, rev. 2.0 132 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 9-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
opcode map mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 133 9.8 opcode map see table 9-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 9-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc908as32a data sheet, rev. 2.0 134 freescale semiconductor central processor unit (cpu) table 9-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 135 chapter 10 external interrupt module (irq) 10.1 introduction this section describes the non-maskable external interrupt (irq) input. 10.2 features features include: dedicated external interrupt pin (irq ) hysteresis buffer programmable edge-only or edge- and level-interrupt sensitivity automatic interrupt acknowledge 10.3 functional description a falling edge applied to the external interrupt pin can latch a cpu interrupt request. figure 10-2 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a 1 to the ack bit clears the irq latch. reset ? a reset automatically clears both interrupt latches. the external interrupt pin is falling-edge triggered and is software configurable to be both falling-edge and low-level triggered. the mode bit in the iscr co ntrols the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to a high level the vector fetch or software clear may occur before or after the interrupt pin returns to a high level. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode1 control bit, thereby clearing the in terrupt even if the pin stays low.
external interrupt module (irq) mc68hc908as32a data sheet, rev. 2.0 136 freescale semiconductor figure 10-1. block diagram highlighting irq block and pins break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
irq pin mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 137 figure 10-2. irq block diagram when set, the imask bit in the iscr masks all exter nal interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the co rresponding imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. refer to figure 10-3 . 10.4 irq pin a falling edge on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge sensitive and low-level sensitive. with mode set, both of the following actions mu st occur to clear the irq latch: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (iscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latc h. writing to the ack bit can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge on irq that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu load s the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to a high level ? as long as the irq pin is low, the irq1 latch remains set. ack imask dq ck clr irq high interrupt to mode select logic irq latch request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus irq
external interrupt module (irq) mc68hc908as32a data sheet, rev. 2.0 138 freescale semiconductor figure 10-3. irq interrupt flowchart the vector fetch or software clear and the return of the irq pin to a high level can occur in any order. the interrupt request remains pending as long as the irq pin is low. a reset will clear the latch and the mode control bit; thereby, clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. from reset i bit set? fetch next yes no interrupt? instruction swi instruction? rti instruction? no stack cpu registers no set i bit load pc with interrupt vector no yes unstack cpu registers execute instruction yes yes
irq module during break interrupts mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 139 10.5 irq module du ring break interrupts the system integration module (sim) controls whether the irq interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latches during the break state. see chapter 15 system integration module (sim) for additional information. to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. 10.6 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has these functions: shows the state of the irq interrupt flag clears the irq interrupt latch masks irq interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001a bit 7654321bit 0 read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 10-4. irq status and control register (iscr)
external interrupt module (irq) mc68hc908as32a data sheet, rev. 2.0 140 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 141 chapter 11 low-voltage inhibit (lvi) 11.1 introduction this section describes the low-voltage inhibi t module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 11.2 features features of the lvi module include: programmable lvi reset programmable power consumption note if a low-voltage interrupt (lvi) occurs during programming of eeprom or flash memory, then adequate programming time may not have been allowed to ensure the integrity and retention of the data. it is the responsibility of the user to ensure that in the event of an lvi any addresses being programmed receive specific ation programming conditions. 11.3 functional description figure 11-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. the lvi power bit, lvipwr, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirst, enables the lvi module to generate a reset when v dd falls below a voltage, lvi tripf , and remains at or below that level for nine or more consecutive cpu cycles. note short v dd spikes may not trip the lvi. it is the user?s responsibility to ensure a clean v dd signal within the specified operating voltage range if normal microcontroller operation is to be guaranteed. lvistop, enables the lvi module during stop mode. this will ensure when the stop instruction is implemented, the lvi will continue to monitor the voltage level on v dd . lvipwr, lvistop, and lvirst are in the configuration register, config1 (see chapter 6 configuration register (config1) ). once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, lvi tripr . v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset (see 11.3.2 forced reset operation ). the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices.
low-voltage inhibit (lvi) mc68hc908as32a data sheet, rev. 2.0 142 freescale semiconductor figure 11-1. lvi module block diagram 11.3.1 polled lvi operation in applications that can operate at v dd levels below the lvi tripf level, software can monitor v dd by polling the lviout bit. in the configuration register , the lvipwr bit must be at 1 to enable the lvi module, and the lvirst bit must be at 0 to disable lvi resets. 11.3.2 forced reset operation in applications that require v dd to remain above the lvi tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the lvi tripf level and remains at or below that level for nine or more consecutive cpu cycles. in the configuration register, the lvip wr and lvirst bits must be at 1 to enable the lvi module and to enable lvi resets. 11.3.3 false reset protection in order for the lvi module to reset the mcu,v dd must remain at or below the lvi tripf level for nine or more consecutive cpu cycles. v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. 11.4 lvi status register the lvi status register flags v dd voltages below the lvi tripf level . address: $fe0f bit 7654321bit 0 read:lviout0000000 write: reset:00000000 = unimplemented figure 11-2. lvi status register (lvisr) low v dd lvirst v dd > lvi trip = 0 v dd < lvi trip = 1 lvi out lvipwr detector v dd lvi reset from config1 from config1 cpu clock anlgtrip stop mode filter bypass from config1 lvistop
lvi interrupts mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 143 lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the lvi tripf voltage (see table 11-1 ). reset clears the lviout bit. 11.5 lvi interrupts the lvi module does not generate interrupt requests. 11.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 11.6.1 wait mode with the lvipwr bit in the configur ation register programmed to 1, the lvi module is active after a wait instruction. with the lvirst bit in the confi guration register programmed to 1, the lvi module can generate a reset and bring the mcu out of wait mode. 11.6.2 stop mode with the lvistop and lvipwr bits in the configuration register prog rammed to a 1, the lvi module will be active after a stop instruction. because cpu cl ocks are disabled during st op mode, the lvi trip will generate a reset and bring the mcu out of stop. with the lvipwr bit in the configuration register programmed to a 1 and the lvistop bit at 0, the lvi module will be inactive a fter a stop instruction. note the lvi feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application v dd voltage collapsing completely to an unsafe level. it is not intended that users operate the microcontroller at lower than the specified operating voltage (v dd ). table 11-1. lviout bit indication v dd lviout at level: v dd > lvi tripr 0 v dd < lv i tripf 1 lv i tripf < v dd < lv i tripr previous value
low-voltage inhibit (lvi) mc68hc908as32a data sheet, rev. 2.0 144 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 145 chapter 12 programmable interrupt timer (pit) 12.1 introduction this section describes the programmable interrupt time r (pit) which is a periodic interrupt timer whose counter is clocked internally via software programmable options. figure 12-1 is a block diagram of the pit. for further information regarding timers on m68hc08 family devices, please consult the hc08 timer reference manual (freescale document order number tim08rm/ad). 12.2 features features include: programmable pit clock input free-running or modulo up-count operation pit counter stop and reset bits 12.3 functional description figure 12-1 shows the structure of the pit. the central component of the pit is the 16-bit pit counter that can operate as a free-running counter or a mo dulo up-counter. the counter provides the timing reference for the interrupt. the pit counter modulo registers, pmodh?pmodl, control the modulo value of the counter. software can read the counter value at any time without affe cting the counting sequence. figure 12-1. pit block diagram prescaler prescaler select internal 16-bit comparator pps2 pps1 pps0 pof poie timpmodh:timpmodl crst cstop 16-bit counter bus clock interrupt logic
programmable interrupt timer (pit) mc68hc908as32a data sheet, rev. 2.0 146 freescale semiconductor 12.4 pit counter prescaler the clock source can be one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits , pps[2:0], in the status and control register select the pit clock source. the value in the pit counter modulo registers and the selected prescaler output determines the frequency of the periodic interrupt. the pit overflow flag (p of) is set when the pit counter value reaches the modulo value programmed in the pi t counter modulo registers. the pit interrupt enable bit, poie, enables pit overflow cpu interrupt requests. pof and poie are in the pit status and control register. 12.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 12.5.1 wait mode the pit remains active after the execution of a wait instruction. in wait mode the pit registers are not accessible by the cpu. any enabled cpu interrupt request from the pit can bring the mcu out of wait mode. if pit functions are not required during wait mode, r educe power consumption by stopping the pit before executing the wait instruction. 12.5.2 stop mode the pit is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the pit counter. pit operation resumes when the mcu exits stop mode after an external interrupt. 12.6 pit during break interrupts a break interrupt stops the pit counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state (see figure 15-18. sim reset status register (srsr) ). to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit.
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 147 12.7 i/o registers the following i/o registers control and monitor operation of the pit: pit status and control register (psc) pit counter registers (pcnth?pcntl) pit counter modulo registers (pmodh?pmodl) 12.7.1 pit status and control register the pit status and control register: enables pit interrupt flags pit overflows stops the pit counter resets the pit counter prescales the pit counter clock pof ? pit overflow flag bit this read/write flag is set when the pit counter reaches the modulo val ue programmed in the pit counter modulo registers. clear pof by reading t he pit status and control register when pof is set and then writing a 0 to pof. if another pit overflow occurs before the clearing sequence is complete, then writing a 0 to pof has no effect. therefore, a pof interrupt request cannot be lost due to inadvertent clearing of pof. reset clears th e pof bit. writing a 1 to pof has no effect. 1 = pit counter has reached modulo value 0 = pit counter has not reached modulo value poie ? pit overflow interrupt enable bit this read/write bit enables pit overflow interr upts when the pof bit becomes set. reset clears the poie bit. 1 = pit overflow interrupts enabled 0 = pit overflow interrupts disabled pstop ? pit stop bit this read/write bit stops the pit counter. counting resumes when pstop is cleared. reset sets the pstop bit, stopping the pit counter until software clears the pstop bit. 1 = pit counter stopped 0 = pit counter active note do not set the pstop bit before entering wait mode if the pit is required to exit wait mode. address: $004b bit 7654321bit 0 read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset:00100000 = unimplemented figure 12-2. pit status and control register (psc)
programmable interrupt timer (pit) mc68hc908as32a data sheet, rev. 2.0 148 freescale semiconductor prst ? pit reset bit setting this write-only bit resets the pit counter and the pit prescaler. setting prst has no effect on any other registers. counting resumes from $0000. prst is cleared automatically after the pit counter is reset and always reads as 0. reset clears the prst bit. 1 = prescaler and pit counter cleared 0 = no effect note setting the pstop and prst bits simultaneously stops the pit counter at a value of $0000. pps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the pit counter as table 12-1 shows. reset clears the pps[2:0] bits. 12.7.2 pit count er registers the two read-only pit counter registers contain the high and low bytes of the value in the pit counter. reading the high byte (pcnth) latches the contents of the low byte (pcntl) into a buffer. subsequent reads of pcnth do not affect the latched pcntl value until pcntl is read. reset clears the pit counter registers. setting the pit reset bit (prst) also clears the pit counter registers. note if you read pcnth during a break interrupt, be sure to unlatch pcntl by reading pcntl before exiting the break interrupt. otherwise, pcntl retains the value latched during the break. table 12-1. prescaler selection pps[2:0] pit clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 internal bus clock 64 address: $004c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 12-3. pit counter registers (pcnth?pcntl)
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 149 12.7.3 pit counter modulo registers the read/write pit modulo registers contain the modulo value for the pit counter. when the pit counter reaches the modulo value the overflow flag (pof) becomes set and the pit counter resumes counting from $0000 at the next timer clock. writing to the hi gh byte (pmodh) inhibits the pof bit and overflow interrupts until the low byte (pmodl) is written. reset sets the pit counter modulo registers. note reset the pit counter before writing to the pit counter modulo registers. address: $004d bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented address: $004e bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 address: $004f bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 12-4. pit counter modulo registers (pmodh?pmodl) figure 12-3. pit counter registers (pcnth?pcntl) (continued)
programmable interrupt timer (pit) mc68hc908as32a data sheet, rev. 2.0 150 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 151 chapter 13 input/output ports 13.1 introduction forty bidirectional input/output (i/o) pins form six parallel ports. all i/o pins are programmable as inputs or outputs. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 13.2 port a port a is an 8-bit general-purpose bidirectional i/o port. 13.2.1 port a data register the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. 13.2.2 data dir ection register a data direction register a determines whether each port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the correspondi ng port a pin; a 0 disables the output buffer. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 13-1. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 13-2. data direction register a (ddra)
input/output ports mc68hc908as32a data sheet, rev. 2.0 152 freescale semiconductor ddra[7:0] ? data direction register a bits these read/write bits contro l port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 13-3 shows the port a i/o logic. figure 13-3. port a i/o circuit when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-1 summarizes the operation of the port a pins. table 13-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x input, hi-z ddra[7:0] pin pta[7:0] (1) 1 x output ddra[7:0] pta[7:0] pta[7:0] (1) x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
port b mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 153 13.3 port b port b is an 8-bit special function port that shares al l of its pins with the analog-to-digital converter (adc). 13.3.1 port b data register the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. atd[7:0] ? adc channels ptb7/atd7?ptb0/atd0 are eight of the adc ch annels. the adc channel select bits, ch[4:0], determine whether the ptb7/atd7?ptb0/atd0 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the data direction for this bi t is programmed as an input. otherwise, the data will reflect the value in the data latch. see chapter 3 analog-to-digital converter (adc) . data direction register b (ddrb) does not affect t he data direction of port b pins that are being used by the adc. however, the ddrb bits always determine whether reading port b returns to the states of the latches or a 0. 13.3.2 data dir ection register b data direction register b determines whether each port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the correspondi ng port b pin; a 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits contro l port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input address: $0001 bit 7 654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative functions: atd7 atd6 atd5 atd4 atd3 atd2 atd1 atd0 figure 13-4. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 13-5. data direction register b (ddrb)
input/output ports mc68hc908as32a data sheet, rev. 2.0 154 freescale semiconductor note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 13-6 shows the port b i/o logic. figure 13-6. port b i/o circuit when bit ddrbx is a 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-2 summarizes the operation of the port b pins. table 13-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x input, hi-z ddrb[7:0] pin ptb[7:0] (1) 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] (1) x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus
port c mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 155 13.4 port c port c is an 5-bit general-purpose bidirectional i/o port. 13.4.1 port c data register the port c data register contains a data latch for each of the five port c pins. ptc[4:0] ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction regi ster c. reset has no effect on ptc[4:0]. mclk ? system clock bit the system clock is driven out of ptc2 when enabled by mclken bit in ptcddr7. 13.4.2 data dir ection register c data direction register c determines whether each port c pin is an input or an output. writing a 1 to a ddrc bit enables the output buffer for the correspondi ng port c pin; a 0 disables the output buffer. mclken ? mclk enable bit this read/write bit enables mclk to be an output signal on ptc2. mclk is the same frquency as the bus clock. if mclk is enabled, ddrc2 has no effect. reset clears this bit. 1 = mclk output enabled 0 = mclk output disabled ddrc[4:0] ? data direction register c bits these read/write bits control port c data direction. reset clears ddrc[4:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. address: $0002 bit 7654321bit 0 read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative functions: mclk = unimplemented figure 13-7. port c data register (ptc) address: $0006 bit 7654321bit 0 read: mclken 00 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 13-8. data direction register c (ddrc)
input/output ports mc68hc908as32a data sheet, rev. 2.0 156 freescale semiconductor figure 13-9 shows the port c i/o logic. figure 13-9. port c i/o circuit when bit ddrcx is a 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-3 summarizes the operation of the port c pins. table 13-3. port c pin functions bit value ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 2 input, hi-z ddrc[2] pin ptc2 1 2 output ddrc[2] 0 ? 0 x input, hi-z ddrc[4:0] pin ptc[4:0] (1) 1 x output ddrc[4:0] ptc[4:0] ptc[4:0] (1) x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus
port d mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 157 13.5 port d port d is an 7-bit general-purpose i/o port. 13.5.1 port d data register port d is a 7-bit special function port that shares seven of its pins with the analog to digital converter and two with the timer interface modules. ptd[6:0] ? port d data bits ptd[6:0] are read/write, software programmable bits . data direction of ptd[6:0] pins are under the control of the corresponding bit in data direction register d. atd[14:8] ? adc channel status bits ptd6/atd14/tclk?ptd0/atd8 are seven of the 15 adc channels. the adc channel select bits, ch[4:0], determine whether the ptd6/atd14/tclk?ptd0/atd8 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the dat a direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch. see chapter 3 analog-to-digital converter (adc) . data direction register d (ddrd) does not affect th e data direction of port d pins that are being used by the tim. however, the ddrd bits always determine whether reading port d returns the states of the latches or a 0. tclk ? timer clock input bit the ptd6/atd14/taclk pin is the external clock input for the timer interface module (tim). the prescaler select bits, ps[2:0], select ptd6/atd14/taclk as the tim clock input. see chapter 17 timer interface module (tim) . when not selected as the tim clock, ptd6/atd14/taclk is available for general-purpose i/o. while tclk is selected corresponding ddrd bits have no effect. 13.5.2 data dir ection register d data direction register d determines whether each port d pin is an input or an output. writing a 1 to a ddrd bit enables the output buffer for the correspondi ng port d pin; a 0 disables the output buffer. address: $0003 bit 7654321bit 0 read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative functions: atd14 atd13 atd12 atd11 atd10 atd9 atd8 tclk = unimplemented figure 13-10. port d data register (ptd)
input/output ports mc68hc908as32a data sheet, rev. 2.0 158 freescale semiconductor ddrd[6:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[6:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note avoid glitches on port d pins by writin g to the port d data register before changing data direction regist er d bits from 0 to 1. figure 13-12 shows the port d i/o logic. figure 13-12. port d i/o circuit when bit ddrdx is a 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-4 summarizes the operation of the port d pins. address: $0007 bit 7654321bit 0 read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 = unimplemented figure 13-11. data direction register d (ddrd) table 13-4. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x input, hi-z ddrd[6:0] pin ptd[6:0] (1) 1 x output ddrd[6:0] ptd[6:0] ptd[6:0] (1) x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus
port e mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 159 13.6 port e port e is an 8-bit special function port that shares two of its pins with the tim, two of its pins with the serial communications interface module (sci), and four of it s pins with the serial peripheral interface module (spi). 13.6.1 port e data register the port e data register contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits pte[7:0] are read/write, software programmable bits . data direction of each port e pin is under the control of the corresponding bit in data direction register e. spsck ? spi serial clock bit the pte7/spsck pin is the serial clock input of an spi slav e module and serial clock output of an spi master module. when the spe bit is clear, the pt e7/spsck pin is availabl e for general-purpose i/o. see chapter 16 serial peripheral interface (spi) . mosi ? master out/slave in bit the pte6/mosi pin is the master out/slave in term inal of the spi module. when the spe bit is clear, the pte6/mosi pin is available for general-purpose i/o. miso ? master in/slave out bit the pte5/miso pin is the master in/slave out te rminal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the pt e5/miso pin is available for general-purpose i/o. see chapter 16 serial peripheral interface (spi) . ss ? slave select bit the pte4/ss pin is the slave select input of the spi module. when the spe bit is clear, or when the spi master bit (spmstr) is set and modfen bit is low, the pte4/ss pin is available for general-purpose i/o. see 16.12.4 ss (slave select) . when the spi is enabled as a slave, the ddrf0 bit in data direction register e (ddre) has no effect on the pte4/ss pin. note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the spi module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 13-5 . address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative functi on: spsck mosi miso ss tch1 tch0 rxd txd figure 13-13. port e data register (pte)
input/output ports mc68hc908as32a data sheet, rev. 2.0 160 freescale semiconductor tch[1:0] ? timer channel i/o bits the pte3/tach1?pte2/tach0 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether t he pte3/tach1?pte2/tach0 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 17 timer interface module (tim) . note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the ti m. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 13-5 . rxd ? sci receive data input bit the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit (ensci) is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. see 14.8.1 sci control register 1 . txd ? sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit (ensci) is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. see 14.8.1 sci control register 1 . note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 13-5 . 13.6.2 data dir ection register e data direction register e determines whether each port e pin is an input or an output. writing a 1 to a ddre bit enables the output buffer for the correspondi ng port e pin; a 0 disables the output buffer. ddre[7:0] ? data direction register e bits these read/write bits contro l port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note avoid glitches on port e pins by writin g to the port e data register before changing data direction regist er e bits from 0 to 1. figure 13-15 shows the port e i/o logic. address: $000c bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 13-14. data direction register e (ddre)
port f mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 161 figure 13-15. port e i/o circuit when bit ddrex is a 1, reading address $0008 reads the ptex data latch. when bit ddrex is a 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-5 summarizes the operation of the port e pins. 13.7 port f port f is a 4-bit special function port that shares four of its pins with the tim. 13.7.1 port f data register the port f data register contains a data latch for each of the four port f pins. ptf[3:0] ? port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the corresponding bit in data direction re gister f. reset has no effect on ptf[3:0]. table 13-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x input, hi-z ddre[7:0] pin pte[7:0] (1) 1 x output ddre[7:0] pte[7:0] pte[7:0] (1) x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. address: $0009 bit 7654321bit 0 read: 0 0 0 0 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset alternative function: tch5 tch4 tch3 tch2 = unimplemented figure 13-16. port f data register (ptf) read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
input/output ports mc68hc908as32a data sheet, rev. 2.0 162 freescale semiconductor tch[5:2] ? timer a channel i/o bits the ptf3?ptf0/tch2 pins are the tim input capture/ output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptf3?ptf0 /tch2 pins are timer channel i/o pins or general-purpose i/o pins. see 17.8.1 tim status and control register . note data direction register f (ddrf) does not affect the data direction of port f pins that are being used by the ti m. however, the ddrf bits always determine whether reading port f returns the states of the latches or the states of the pins. see table 13-6 . 13.7.2 data dir ection register f data direction register f determines whether each port f pin is an input or an output. writing a 1 to a ddrf bit enables the output buffer fo r the corresponding port f pin; a 0 disables the output buffer. ddrf[3:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[3:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input note avoid glitches on port f pins by writ ing to the port f data register before changing data direction regist er f bits from 0 to 1. figure 13-18 shows the port f i/o logic. figure 13-18. port f i/o circuit address: $000d bit 7654321bit 0 read: 0 0 0 0 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 = unimplemented figure 13-17. data direction register f (ddrf) read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus
port f mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 163 when bit ddrfx is a 1, reading address $0009 reads the ptfx data latch. when bit ddrfx is a 0, reading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 13-6 summarizes the operation of the port f pins. table 13-6. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0 x input, hi-z ddrf[3:0] pin ptf[3:0] (1) 1 x output ddrf[3:0] ptf[3:0] ptf[3:0] (1) x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input.
input/output ports mc68hc908as32a data sheet, rev. 2.0 164 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 165 chapter 14 serial communications interface (sci) 14.1 introduction the serial communications interface (sci) allows as ynchronous communications with peripheral devices and other mcus. 14.2 features features include: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 166 freescale semiconductor figure 14-1. block diagram highlighting sci block and pins 14.3 pin name conventions the generic names of the sci input/output (i/o) pins are: rxd (receive data) txd (transmit data) sci i/o lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output reflects the name of the shared port pin. table 14-1 shows the full names and the generic names of the sci i/o pins. the generic pin names appear in the text of this section. table 14-1. pin name conventions generic pin names rxd txd full pin names pte1/scrxd pte0/sctxd break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 167 14.4 functional description figure 14-2 shows the structure of the sci module. the sc i allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices , including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 14-2. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud rate generator cgmxclk rxd txd
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 168 freescale semiconductor 14.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 14-3 . figure 14-3. sci data formats 14.4.2 transmitter figure 14-4 shows the structure of the sci transmitter. figure 14-4. sci transmitter bit 5 start bit bit 0 bit 1 next stop bit start bit start bit bit 0 next stop bit start bit bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit 8-bit data format (bit m in scc1 clear) 9-bit data format (bit m in scc1 set) pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register tc sctie tcie scte transmitter cpu m ensci loops te pte0/txd txinv internal bus 4 pre- scaler scp1 scp0 scr1 scr2 scr0 baud divider 16 cgmxclk interrupt request
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 169 14.4.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9- bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 14.4.2.2 character transmission during an sci transmission, the transmit shift register sh ifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the tr ansmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit (scte) by fi rst reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of 1s. after the preamble shifts out, cont rol logic transfers the s cdr data into the transmit shift register. a 0 start bit automatically goes into t he least significant bit position of the transmit shift register. a 1 stop bit goes into t he most significant bit position. the sci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, 1. if at any time software clears the ensci bit in sci c ontrol register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. 14.4.2.3 break characters writing a 1 to the send break bit, sbk, in scc2 loads t he transmit shift register with a break character. a break character contains all 0s and has no start, st op, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at 1, transmitte r logic continuously loads br eak characters into the transmit shift register. after software clears the sbk bi t, the shift register finish es transmitting the last break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bi t is followed by eight or nine 0 data bits and a 0 where the stop bit should be. receiving a break char acter has the following effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 170 freescale semiconductor 14.4.2.4 idle characters an idle character contains all 1s and has no start, st op, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when a break sequence is followed immedi ately by an idle character, this sci design exhibits a condition in wh ich the break character length is reduced by one half bit time. in this instance, the break sequence will consist of a valid start bit, eight or ni ne data bits (as defined by the m bit in scc1) of 0 and one half data bit length of 0 in the stop bit position followed immediately by the idle character. to ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. note when queueing an idle character, return the te bit to 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. a good time to toggle the te bit for a queued idle character is when the scte bit becomes set and just before writing the next byte to the scdr. 14.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control regi ster 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, st art, and stop bits, are inverted when txinv is at a 1. see 14.8.1 sci control register 1 . 14.4.2.6 transmitter interrupts the following conditions can generate cpu in terrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 14.4.3 receiver figure 14-5 shows the structure of the sci receiver.
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 171 14.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit data . the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). figure 14-5. sci receiver block diagram all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie wakeup logic parity checking msb sci data register r8 orie neie feie peie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 4 16 scp1 scp0 scr1 scr2 scr0 cgmxclk pte1/rxd error cpu interrupt request scrie scrf ilie idle scrie ilie cpu interrupt request all 1s
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 172 freescale semiconductor 14.4.3.2 character reception during an sci reception, the receive shift register shi fts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if th e sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 14.4.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 14-6 ): after every start bit after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit oc curs, the rt clock begins to count to 16. figure 14-6. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 14-2 summarizes the results of the start bit verification samples. table 14-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 173 start bit verification is not successful if any two of the three verification samples are 1s. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-3 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-4 summarizes the results of the stop bit samples. 14.4.3.4 framing errors if the data recovery logic does not detect a 1 where t he stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at the same time that the scrf bit is set. table 14-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 174 freescale semiconductor 14.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 14-7 shows how much a slow receiv ed character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 inst ead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-7 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. figure 14-7. slow data the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-7 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% =
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 175 fast data tolerance figure 14-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 14-8. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-8 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 14.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes th e receiver from the standby state by clearing the rwu bit. the address mark also sets the sc i receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90% = 170 176 ? 170 ------------------------- - 100 3.53% =
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 176 freescale semiconductor idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 14.4.3.7 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 14.4.3.8 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when t he sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in s cc3 enables pe to generate sci error cpu interrupt requests. 14.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 14.5.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not accessible by the cpu. any enabl ed cpu interrupt request from the sci module can bring the mcu out of wait mode.
sci during break module interrupts mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 177 if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 14.5.2 stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. 14.6 sci during br eak module interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 14.7 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: pte0/txd ? transmit data pte1/rxd ? receive data 14.7.1 pte0/sctxd (transmit data) the pte0/txd pin is the serial data output from t he sci transmitter. the sci shares the pte0/txd pin with port e. when the sci is enabled , the pte0/txd pin is an output re gardless of the state of the ddre2 bit in data direction register e (ddre). 14.7.2 pte1/scrxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with port e. when the sci is enabled, the pte1/rxd pin is an i nput regardless of the state of the ddre1 bit in data direction register e (ddre).
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 178 freescale semiconductor 14.8 i/o registers the following i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 14.8.1 sci cont rol register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake illty pen pty write: reset:00000000 figure 14-9. sci control register 1 (scc1)
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 179 txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit inverts all tran smitted values, including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether sci char acters are eight or nine bits long. see table 14-5 .the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which condition wa kes up the sci: a 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recognition , but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the sci parity function (see table 14-5 ). when enabled, the parity function inserts a parity bit in the most significant bit position (see table 14-4 ). reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the sci gener ates and checks for odd pari ty or even parity (see table 14-5 ). reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error.
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 180 freescale semiconductor 14.8.2 sci cont rol register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to gener ate sci transmitter cpu interrupt requests. setting the sctie bit in scc3 enables the scte bit to generate cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests table 14-5. character format selection control bits character format m pen and pty start bits data bi ts parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 14-10. sci control register 2 (scc2)
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 181 scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. setting the scrie bit in scc3 enables the scrf bit to generat e cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the txd pin. if softw are clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowe d when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a 1. the 1 after the break character guarantees recogni tion of a valid start bit. if sbk remains set, the transmitter continuously transmits break c haracters with no 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble.
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 182 freescale semiconductor 14.8.3 sci cont rol register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted. enables the following interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the re ad-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a co py of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. rese t has no effect on the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:uu000000 = unimplemented r = reserved u = unaffected figure 14-11. sci control register 3 (scc3)
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 183 14.8.4 sci status register 1 sci status register 1 contains flags to signal the following conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt reques t. in normal operation, clear the scte bit by reading scs1 with scte set and then wr iting to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency be tween queueing data, preamble, and break and the transmission actually starti ng. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set the scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an sci receiver cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 14-12. sci status register 1 (scs1)
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 184 freescale semiconductor receive a valid character that sets the scrf bit befo re an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character mu st again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 14-13 shows the normal flag-clearing sequenc e and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. figure 14-13. flag clearing sequence byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 185 nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is al so set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is se t. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected 14.8.5 sci status register 2 sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again on ly after 1s appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling address: $0017 bit 7654321bit 0 read:000000bkfrpf write: reset:00000000 = unimplemented figure 14-14. sci status register 2 (scs2)
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 186 freescale semiconductor rpf before disabling the sci module or entering st op mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress 14.8.6 sci data register the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $0018 accesses the read-only rece ived data bits, r7:r0. writing to address $0018 writes the data to be transmitted, t7:t0. reset has no effect on the sci data register. note do not use read-modify-write instructions on the sci data register. 14.8.7 sci baud rate register the baud rate register selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 14-6 . reset clears scp1 and scp0. address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-15. sci data register (scdr) address: $0019 bit 7654321bit 0 read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: reset:00000000 = unimplemented figure 14-16. sci baud rate register (scbr) table 14-6. sci baud rate prescaling scp[1:0] prescaler divisor (pd) 00 1 01 3 10 4 11 13
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 187 scr2 ? scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 14-7 . reset clears scr2?scr0. use the following formula to calculate the sci baud rate: where: f crystal = crystal frequency pd = prescaler divisor bd = baud rate divisor table 14-8 shows the sci baud rates that can be generated with a 4.9152-mhz crystal. table 14-7. sci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f crystal 64 pd bd ------------------------------------ =
serial communications interface (sci) mc68hc908as32a data sheet, rev. 2.0 188 freescale semiconductor table 14-8. sci baud rate selection examples scp[1:0] prescaler divisor (pd) scr[2:1:0] baud rate divisor (bd) baud rate (f crystal = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 189 chapter 15 system integration module (sim) 15.1 introduction this section describes the system integration module (sim), which supports up to 32 external and/or internal interrupts. together with the central proces sor unit (cpu), the sim cont rols all mcu activities.the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing a block diagram of the sim is shown in figure 15-2 . table 15-1 shows the internal signal names used in this section. table 15-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 190 freescale semiconductor figure 15-1. block diagram highlighting sim block and pins 15.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an in coming clock, cgmout, as shown in figure 15-3 . this clock can come from either an external oscillator or from the on-chip phase-lock loop (pll). see chapter 5 clock generator module (cgm) . 15.2.1 bus timing in user mode , the internal bus frequency is either the crys tal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. see chapter 5 clock generator module (cgm) . break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
sim bus clock control and generation mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 191 figure 15-2. sim block diagram figure 15-3. cgm clock signals stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter ptc3 monitor mode clock select circuit cgmvclk bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 192 freescale semiconductor 15.2.2 clock startup fr om por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an i nactive phase until after 4096 cgmxclk cycles. the rst pin is driven low by the sim during this entire per iod. the bus clocks start upon completion of the timeout. 15.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. see 15.6.2 stop mode . in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 15.3 reset and s ystem initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 15.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr) (see 15.7 sim registers ). 15.3.1 external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for at least the minimum t rl time. figure 15-4 shows the relative timing. figure 15-4. external reset timing rst iab pc vect h vect l cgmout
reset and system initialization mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 193 15.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles (see figure 15-5 ). an internal reset can be caused by an i llegal address, illegal opcode, cop timeout, lvi, or por (see figure 15-6 ). note that for lvi or por rese ts, the sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 15-5 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. figure 15-5. internal reset timing figure 15-6. sources of internal reset table 15-2. reset recovery timing reset recovery type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 194 freescale semiconductor 15.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. another sixty-four cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. see figure 15-7 . at power-on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. figure 15-7. por recovery 15.3.2.2 computer operating properly (cop) reset the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr) if the copd bit in the config1 register is at 0. see chapter 8 computer operating properly (cop) . 15.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the config1 register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff
sim counter mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 195 15.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. warning extra care should be exercised if code in this part has been migrated from older hc08 devices since the illegal address reset specification may be different. also, extra care should be exercised when using this emulation part for development of code to be run in rom az, ab or as family parts with a smaller memory size since some legal addresses will become illegal addresses on the smaller rom memory map device and may as a result generate unwanted resets. 15.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the v lvii voltage. the lvi bit in the sim reset status register (srsr) is set and a chip reset is asserted if the lvipwrd and lvirstd bits in the config1 register are at 0. the rst pin will be held low until the sim counts 4096 cgmxclk cycles after v dd rises above v lvir . another sixty-four cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. see chapter 11 low-voltage inhibit (lvi) . 15.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly mo dule (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bits long and is clock ed by the falling edge of cgmxclk. 15.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the clock generation module (cgm) to drive the bus clock state machine. 15.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt or reset, the sim senses the state of the short stop recovery bit, ssrec, in the config1 register. if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxcl k cycles. this is ideal for appl ications using c anned oscillators that do not require long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared.
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 196 freescale semiconductor 15.4.3 sim counter and reset states external reset has no effect on the sim counter. see 15.6.2 stop mode for details. the sim counter is free-running after all reset states. see 15.3.2 active resets from internal sources for counter control and internal reset recovery sequences. 15.5 program exception control normal, sequential program execution can be changed in three different ways: 1. interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) 2. reset 3. break interrupts 15.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 15-8 shows interrupt entry timing. figure 15-10 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared), see figure 15-9 . figure 15-8 . interrupt entry module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit
program exception control mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 197 figure 15-9. interrupt processing no no no yes no no yes yes (as many interrupts i bit set? from reset break interrupt? i bit set? irq1 interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes as exist on chip)
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 198 freescale semiconductor figure 15-10. interrupt recovery hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the si m proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an inst ruction execution, the highest priority interrupt is serviced first. figure 15-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m68hc05, m6805 and m146805 families the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. figure 15-11 . interrupt recognition example idb r/w module interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
low-power modes mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 199 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 15.5.2 reset all reset sources always have higher priority than interrupts and cannot be arbitrated. 15.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. see 18.2 break module (brk) . the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 15.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 15.6 low-power modes executing the wait or stop instruction puts the mcu in a low power- consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 15.6.1 wait mode in wait mode, the cpu clocks are inactive while one set of peripheral clocks continue to run. figure 15-12 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode.
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 200 freescale semiconductor wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break wait bit, bw, in the sim break status register (sbsr ). if the cop disable bit, co pd, in the configuration register is 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 15-12. wait mode entry timing figure 15-13. wait recovery from interrupt or break figure 15-14. wait recovery from internal reset wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles
low-power modes mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 201 15.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset also caus es an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is se lectable using the ssrec bit in the configuration register (config1). if ssrec is set, stop recove ry is reduced from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal fo r applications using canned oscillators that do not require long startup times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit. the break module is inactive in stop mode. the stop instruction does not affect break module register states. the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 15-15 shows stop mode entry timing. note to minimize stop current, all pins conf igured as inputs should be driven to a logic 1 or logic 0. figure 15-15. stop mode entry timing figure 15-16. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction . cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 202 freescale semiconductor 15.7 sim registers the sim has three memory mapped registers. 15.7.1 sim break st atus register the sim break status register contains a flag to i ndicate that a break caused an exit from wait mode. bw ? sim break wait this status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. clear bw by writing a 0 to it. reset clears bw. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 15.7.2 sim reset status register the srsr register contains flags that show the s ource of the last reset. the status register will automatically clear after reading srsr. a power-on rese t sets the por bit and clears all other bits in the register. all other reset sources set the individual fl ag bits but do not clear the register. more than one reset source can be flagged at any time depending on the c onditions at the time of the internal or external reset. for example, the por and lvi bit can both be set if the power supply has a slow rise time. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr address: $fe00 bit 7654321bit 0 read: rrrrrr bw r write: see note reset: 0 r = reserved note: writing a 0 clears bw figure 15-17. sim break status register (sbsr) address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 = unimplemented figure 15-18. sim reset status register (srsr)
sim registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 203 ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr 15.7.3 sim break flag control register the sim break control register contains a bit that e nables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 15-19. sim break flag control register (sbfcr)
system integration module (sim) mc68hc908as32a data sheet, rev. 2.0 204 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 205 chapter 16 serial peripheral interface (spi) 16.1 introduction this section describes the serial peripheral interfac e (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 16.2 features features of the spi module include: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts with cpu service: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated circuit) compatibility 16.3 pin name and regi ster name conventions the generic names of the spi input/output (i/o) pins are: ss (slave select) spsck (spi serial clock) mosi (master out slave in) miso (master in slave out) the spi shares four i/o pins with a parallel i/o port. the full name of an spi pin reflects the name of the shared port pin. table 16-1 shows the full names of the spi i/o pins. the generic pin names appear in the text that follows. table 16-1. pin name conventions spi generic pin name miso mosi ss spsck full spi pin name pte5/miso pte6/mosi pte4/ss pte7/spsck
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 206 freescale semiconductor figure 16-1. block diagram highlighting spi block and pins the generic names of the spi i/o registers are: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 207 16.4 functional description figure 16-2 shows the structure of the spi module. the spi module allows full-dupl ex, synchronous, serial communica tion between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt driven. all spi interrupts can be serviced by the cpu. the following paragraphs describe the operation of the spi module. figure 16-2. spi module block diagram transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus bus clock modfen errie control modf spmstr mosi miso spsck ss
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 208 freescale semiconductor 16.4.1 master mode the spi operates in master mode when the spi master bit, spmstr (spcr $0010), is set. note configure the spi modules as mast er and slave before enabling them. enable the master spi before enabling t he slave spi. disable the slave spi before disabling the master spi. see 16.13.1 spi control register . only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte (spscr $0011). the byte begins shifting out on the mosi pin under the control of the serial clock. see table 16-2 . the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register (see 16.13.2 spi status and control register ). through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. figure 16-3. full-duplex master-slave connections as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends wh en the receiver full bit, sprf (spscr), becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears spr f by reading the spi status and control register and then reading the spi data register. writing to the spi data register clears the sptie bit. 16.4.2 slave mode the spi operates in slave mode when the spmstr bi t (spcr, $0010) is clear. in slave mode the spsck pin is the input for the serial cl ock from the master mcu. before a data transmission occurs, the ss pin of the slave mcu must be low. ss must remain low until the transmission is complete. see 16.6.2 mode fault error . in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it is transferred to the receive data register, and the sprf bit (spscr) is set. to prev ent an overflow condition, slave software then must read the spi data register before another byte enters the shift register. shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
transmission formats mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 209 the maximum frequency of the spsck for an spi confi gured as a slave is the bus clock speed, which is twice as fast as the fastest master spsck clock that can be generated. the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at l east one bus cycle before the master starts the next transmission. otherwise the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 16.5 transmission formats . if the write to the data register is late, the spi transm its the data already in the shift register from the previous transmission. note to prevent spsck from appearing as a clock edge, spsck must be in the proper idle state before the slave is enabled. 16.5 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock line synchronizes shifti ng and sampling on the two serial data lines. a slave select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi dev ice, the slave select line can be used optionally to indicate a multiple-master bus contention. 16.5.1 clock phase and polarity controls software can select any of four combinations of seri al clock (sck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no signifi cant effect on the transmission format. the clock phase (cpha) control bit (spcr) select s one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the pha se and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note before writing to the cpol bit or the cpha bit (spcr), disable the spi by clearing the spi enable bit (spe).
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 210 freescale semiconductor 16.5.2 transmission format when cpha = 0 figure 16-4 shows an spi transmission in which cpha (spc r) is 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), an d master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi (see 16.6.2 mode fault error ). when cpha = 0, the first spsck edge is the msb c apture strobe. therefore, the slave must begin driving its data before the first spsc k edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low again between each byte transmitted. figure 16-4. transmission format (cpha = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol = 1 mosi from master miso from slave ss to slave capture strobe
transmission formats mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 211 16.5.3 transmission format when cpha = 1 figure 16-5 shows an spi transmission in which cpha (sp cr) is 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), an d master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi (see 16.6.2 mode fault error ). when cpha = 1, the master begins driving its mo si pin on the first spsc k edge. therefore, the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 16-5. transmission format (cpha = 1) 16.5.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), transmissions are started by a software write to the spdr ($0012). cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the sck signal. when cpha = 0, the sck si gnal remains inactive for the first half of the first sck cycle. when cpha = 1, the first sck cycle begins with an edge on the sck line from its inactive to its active level. the spi clock rate (selected by spr1?spr0) affects the delay from the write to spdr and the start of the spi transmission (see figure 16-6 ). the internal spi clock in the master is a free-running derivative of the inter nal mcu clock. it is only enabled when both the spe and spmstr bits (spcr) are set to conserve power. sck edges occur half way through the low time of the internal mcu clock. since the spi clock is free-running, it is unce rtain where the write to the spdr will occur relative to the slower sck. this uncertainty causes t he variation in the initiation delay shown in figure 16-6 . this bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol =1 mosi from master miso from slave ss to slave capture strobe
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 212 freescale semiconductor delay will be no longer than a single spi bit time. that is, the maximum delay between the write to spdr and the start of the spi transmission is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. figure 16-6. transmission start delay (master) write to spdr initiation delay bus mosi sck cpha = 1 sck cpha = 0 sck cycle number msb bit 6 12 clock write to spdr earliest latest sck = internal clock 2; earliest latest 2 possible start points sck = internal clock 8; 8 possible start points earliest latest sck = internal clock 32; 32 possible start points earliest latest sck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? ? ? initiation delay from write spdr to transfer begin
error conditions mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 213 16.6 error conditions two flags signal spi error conditions: 1. overflow (ovrf in spscr) ? faili ng to read the spi data register bef ore the next byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the spi data register. ovrf is in the spi status and control register. 2. mode fault error (modf in spscr) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. mo df is in the spi status and control register. 16.6.1 overflow error the overflow flag (ovrf in spscr) becomes set if t he spi receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next tr ansmission occurs. (see figure 16-4 and figure 16-5 .) if an overflow occurs, the data bei ng received is not transferred to the receive data register so that the unread data can still be read. therefore, an overflow error always indicates the loss of data. ovrf generates a receiver/error cp u interrupt request if the error in terrupt enable bit (errie in spscr) is also set. modf and ovrf can generate a receiver/error cpu interrupt request (see figure 16-9 ). it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if an end-of-block transmission interrupt was meant to pull the mcu out of wait, having an overflow condition without overflow interr upts enabled causes the mcu to hang in wait mode. if the ovrf is enabled to generate an interrupt, it can pull the mcu out of wait mode instead. if the cpu sprf interrupt is enabled and the ovrf in terrupt is not, watch for an overflow condition. figure 16-7 shows how it is possi ble to miss an overflow. the first part of figure 16-7 shows how to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf flag can be set in between the time that spscr and spdr are read. in this case, an overflow can be easily missed. since no more sprf interrupts can be generated until this ovrf is serviced, it will not be obvious that bytes ar e being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr after the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions will comple te with an sprf interrupt. figure 16-8 illustrates this pr ocess. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit (spscr).
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 214 freescale semiconductor figure 16-7. missed read of overflow condition figure 16-8. clearing sprf when ovrf interrupt is not enabled read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscrw with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is set. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear.
error conditions mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 215 16.6.2 mode fault error for the modf flag (in spscr) to be set, the mode fault error enable bit (modfen in spscr) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie in spscr) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. modf and ovrf can generate a receiver/error cpu interrupt request (see figure 16-9 ). it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (mod fen) set, the mode fault flag (modf) is set if ss is low. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note to prevent bus contention with another master spi after a mode fault error, clear all data direction register (ddr ) bits associated with the spi shared port pins. setting the modf flag (spscr) does not clear the spmstr bit. reading spmstr when modf = 1 will indicate a mode fault error occurred in either master mode or slave mode. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once t he incoming spsck returns to its idle level after the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level after the shift of the last data bit (see 16.5 transmission formats ). note when cpha = 0, a modf occurs if a slave is selected (ss is low) and later deselected (ss is high) even if no spsck is sent to that slave. this happens because ss is low indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later deselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bi t or reset the spi in any way. software can abort the spi transmission by toggling the spe bit of the slave. note a high voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if a transmission has begun.
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 216 freescale semiconductor to clear the modf flag, read the spscr and then wr ite to the spcr register. this entire clearing procedure must occur with no modf condition existing or else the flag will not be cleared. 16.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests: the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests. the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt, provided that the spi is enabled (spe = 1). the error interrupt enable bit (errie) enables both the modf and ovrf flags to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf flag is enabled to generate receiver/error cpu interrupt requests. figure 16-9. spi interrupt request generation two sources in the spi status and control register can generate cpu interrupt requests: 1. spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf can generate an spi receiver/error cpu interrupt request. 2. spi transmitter empty (spte) ? the spte bit becom es set every time a by te transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte can generate an spte cpu interrupt request. table 16-2. spi interrupts flag request spte (transmitter empty) spi transmi tter cpu interrupt request (sptie = 1) sprf (receiver full) spi receiver cpu interrupt request (sprie = 1) ovrf (overflow) spi receiver/error in terrupt request (sprie = 1, errie = 1) modf (mode fault) spi receiver/error interrupt request (sprie = 1, errie = 1, modfen = 1) spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request
queuing transm ission data mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 217 16.8 queuing tr ansmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag ( spte in spscr) indicates when the transmit data buffer is ready to accept new data. write to the spi data register only when the spte bit is high. figure 16-10 shows the timing associated wi th doing back-to-back transmissi ons with the spi (spsck has cpha:cpol = 1:0). figure 16-10. sprf/spte cpu interrupt timing for a slave, the transmit data buffer allows back-to-b ack transmissions to occur without the slave having to time the write of its data between the transmissions. also, if no new data is written to the data buffer, the last value contained in the shift regi ster will be the next data word transmitted. bit 3 mosi spsck (cpha:cpol = 1:0) spte write to spdr 1 cpu writes byte 2 to spdr, queueing cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift register 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 byte 2 and clearing spte bit. register to shift register, setting spte bit. to receive data register, setting sprf bit. byte 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set.
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 218 freescale semiconductor 16.9 resetting the spi any system reset completely resets the spi. partia l reset occurs whenever th e spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logic is defaul ted back to being general-purpose i/o. the following additional items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr regist er (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to reset all control bits when spe is set back to high fo r the next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi also can be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. 16.10 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.10.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode, the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occu rs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). see 16.7 interrupts . 16.10.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after the mcu exits stop mode. if stop mode is exited by reset, any transfer in progress is aborted and the spi is reset. 16.11 spi during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr, $fe03) enables software to clear status bits during the break state. see 15.7.3 sim break flag control register .
i/o signals mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 219 to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the data register in break mode will not initiate a transmission nor will this data be transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 16.12 i/o signals the spi module has four i/o pins and shares three of them with a parallel i/o port. miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select v ss ? clock ground the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 16.12.1 miso (mas ter in/slave out) miso is one of the two spi module pins that transmit serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is 0 and its ss pin is low. to support a multiple-slave system, a 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the st ate of the data direction register of the shared i/o port. 16.12.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmit serial data. in full-duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port.
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 220 freescale semiconductor 16.12.3 spsck (serial clock) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi contro ls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 16.12.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission (see 16.5 transmission formats ). since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low throughout the transmission for the cpha = 1 format. see figure 16-11 . figure 16-11. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. see 16.13.2 spi status and control register . note a high voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if a transmission already has begun. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck (see 16.6.2 mode fault error ). for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the data register. see table 16-3 . table 16-3. spi configuration spe spmstr modfen spi configuration state of ss logic 0 x x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input only to spi x = don?t care byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 221 16.12.5 v ss (clock ground) v ss is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize r adio frequency (rf) emissions, connect the ground pin of the slave to the v ss pin. 16.13 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) 16.13.1 spi control register the spi control register: enables spi module interrupt requests selects cpu interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the sh ift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 16-4 and figure 16-5 .) to transmit data between spi modules, the spi modules must have identical cpol bits. reset clears the cpol bit. address: $0010 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r= reserved figure 16-12. spi control register (spcr)
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 222 freescale semiconductor cpha ? clock phase bit this read/write bit controls the timing relati onship between the serial clock and spi data. (see figure 16-4 and figure 16-5 .) to transmit data between spi modules, the spi modules must have identical cpha bits. when cpha = 0, the ss pin of the slave spi module must be set to 1 between bytes. (see figure 16-11 ). reset sets the cpha bit. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the data register. therefore, the slave data register must be loaded with the desired transmit data before the falling edge of ss . any data written after the falling edge is stored in the dat a register and transferred to the shift register at the current transmission. when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in certain cases, it may also cause the modf flag to be set (see 16.6.2 mode fault error ). a 1 on the ss pin does not in any way affect the state of the spi state machine. spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mos i, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins spe ? spi enable bit this read/write bit enables the spi module. clear ing spe causes a partial reset of the spi (see 16.9 resetting the spi ). reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie ? spi transmit interrupt enable bit this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 16.13.2 spi status and control register the spi status and control register contai ns flags to signal t he following conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also c ontains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 223 sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. any read of the spi data register clears the sprf bit. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read-only bit enables the modf and ovrf flags to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and t hen reading the spi data register. reset clears the ovrf flag. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission. in a master spi, the modf flag is set if the ss pin goes low at any time. clear the modf bit by reading the spi status and control register with modf set and then writing to the spi data register. reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note do not write to the spi data register unless the spte bit is high. address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 16-13. spi status and control register (spscr)
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 224 freescale semiconductor for an idle master or idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since t he transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already ac tive slave, the load of the shift register cannot occur until the transmission is completed. this impl ies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not av ailable as a general pur pose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-pu rpose i/o regardless of the value of modfen. see 16.12.4 ss (slave select) . if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. see 16.6.2 mode fault error . spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 16-4 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm), see chapter 5 clock generator module (cgm) . bd = baud rate divisor table 16-4. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- =
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 225 16.13.3 spi data register the spi data register is the read/write buffer for the receive data register and the transmit data register. writing to the spi data register writes data into the transmit data register. r eading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate buffers that can contain different values. see figure 16-2 . r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructio ns on the spi data register since the buffer read is not the same as the buffer written. address: $0012 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 16-14. spi data register (spdr)
serial peripheral interface (spi) mc68hc908as32a data sheet, rev. 2.0 226 freescale semiconductor
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 227 chapter 17 timer interface module (tim) 17.1 introduction this section describes the timer interface module (t im). the tim is a 6-channel timer that provides a timing reference with input capture, output compare, and pulse-width- modulation functions. figure 17-2 is a block diagram of the tim. for further information regarding timers on m68hc08 family devices, please consult the hc08 timer reference manual , (freescale document order number tim08rm/ad). 17.2 features features include: six input capture/output compare channels ? rising-edge, falling-edge or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? seven frequency internal bus clock prescaler selection ? external tim clock input (4 mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 17.3 functional description figure 17-2 shows the tim structure. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-count er. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh?tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the six tim channels are programmable independently as input capture or output compare channels. 17.3.1 tim counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, ptd6/atd14/tclk. the prescaler generates seven cl ock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source.
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 228 freescale semiconductor figure 17-1. block diagram highlighting tim block and pins break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 229 figure 17-2. tim block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a pte2 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock ptd6/atd14/tclk pte2/tch0 pte3/tch1 ptf0/tch2 ptf1/tch3 logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a pte3 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic 16-bit comparator 16-bit latch tch2h:tch2l ms2a els2b els2a ptf0 channel 2 tov2 ch2ie ch2f ch2max ms2b logic inter- rupt logic 16-bit comparator 16-bit latch tch3h:tch3l ms3a els3b els3a ptf1 channel 3 tov3 ch3ie ch3f ch3max logic inter- rupt logic 16-bit comparator 16-bit latch tch4h:tch4l ms4a els4b els4a ptf2 channel 4 tov4 ch4ie ch4f ch5max ms4b logic inter- rupt logic 16-bit comparator 16-bit latch tch5h:tch5l ms5a els5b els5a ptf3 channel 5 tov5 ch5ie ch5f ch5max logic inter- rupt logic ptf2/tch4/tch4 ptf3/tch5/tch5
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 230 freescale semiconductor 17.3.2 input capture an input capture function has thr ee basic parts: edge select logic, an input capture latch, and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the correspondi ng input capture edge detector senses a defined transition. the polarity of the active edge is programma ble. the level transition which triggers the counter transfer is defined by the corresponding input ed ge bits (elsxb and elsxa in tsc0?tsc5 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh?tchxl. input captures can generate tim cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. the free-running counter contents are transferred to the tim channel register (tchxh?tchxl see 17.8.5 tim channel registers ) on each proper signal transition regardless of whether the tim channel flag (ch0f?ch5f in tsc0?tsc5 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register 2 bus cy cles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a perio d, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establis h a time reference. in this case, an input capture function is used in conjuncti on with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 17.8.5 tim channel registers ). because both input captures and output compares are refer enced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the tim channel registers. 17.3.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear or toggle the cha nnel pin. output compares can generate tim cpu interrupt requests. 17.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 17.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written.
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 231 use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 17.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte2/tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 regist ers initially controls the output on the pte2/tch0 pin. writing to the tim channel 1 registers enables th e tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the ptf0/tch2 pin. the tim channel registers of the linked pair alternately control the output. setting the ms2b bit in tim channel 2 status and control register (tsc 2) links channel 2 and channel 3. the output compare value in the tim channel 2 regist ers initially controls the output on the ptf0/tch2 pin. writing to the tim channel 3 registers enables th e tim channel 3 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (2 or 3) that control the output are the ones written to last. ts c2 controls and monitors the buffered output compare function, and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tch3, is avai lable as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the ptf2/tch4 pin. the tim channel registers of the linked pair alternately control the output. setting the ms4b bit in tim channel 4 status and control register (tsc 4) links channel 4 and channel 5. the output compare value in the tim channel 4 regist ers initially controls the output on the ptf2/tch4 pin. writing to the tim channel 5 registers enables the tim channel 5 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (4 or 5) that control the output are the ones written to last. ts c4 controls and monitors the buffered output compare function and tim channel 5 status and control register (tsc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3/tch5, is avai lable as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares.
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 232 freescale semiconductor 17.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the valu e in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 17-3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is 1. program the tim to set the pin if the state of the pwm pulse is 0. figure 17-3. pwm period and pulse width the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 17.8.1 tim status and control register ). the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 17.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 17.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written to the tim channel registers. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. ptex/ptfx/tchx period pulse width overflow overflow overflow output compare output compare output compare
functional description mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 233 when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 17.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte2/tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the pte2/tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf0/tch2 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tim channel 2 status and control register (tsc 2) links channel 2 and channel 3. the tim channel 2 registers initially control the pulse width on the ptf0/tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent ov erflow, the tim channel registers (2 or 3) that control the pulse width are the ones written to last. tsc2 controls and monitors the buffered pwm function and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tch3, is availabl e as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered pwm channel whose output appears on the ptf2/tch4 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms4b bit in tim channel 4 status and control register (tsc 4) links channel 4 and channel 5. the tim channel 4 registers initially control the pulse width on the ptf2/tch4 pin. writing to the tim channel 5 registers enables the tim channel 5 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent ov erflow, the tim channel registers (4 or 5) that control the pulse width are the ones written to last. tsc4 controls and monitors the buffered pwm function and tim channel 5 status and control register (tsc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3/tch5, is availabl e as a general-purpose i/o pin.
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 234 freescale semiconductor note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 17.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh? tmodl) write the value for the required pwm period. 3. in the tim channel x registers (tchxh?tchxl) write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb?msxa (see table 17-2 ). b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level (see table 17-2 ). note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc) clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h?tch0l) initially contro l the buffered pwm output. tim status control register 0 (tsc0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tim channel 2 registers (tch2h?tch2l) initially contro l the buffered pwm output. tim status control register 2 (tsc2) controls and monitors the pwm si gnal from the linked channels. ms2b takes priority over ms2a. setting ms4b links channels 4 and 5 and configures them for buffered pwm operation. the tim channel 4 registers (tch4h?tch4l) initially contro l the buffered pwm output. tim status control register 4 (tsc4) controls and monitors the pwm si gnal from the linked channels. ms4b takes priority over ms4a.
interrupts mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 235 clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output (see 17.8.4 tim channel status and control registers ). 17.4 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch5f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interr upt requests are controlled by the channel x interrupt enable bit, chxie. 17.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 17.5.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 17.5.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim c ounter. tim operation resumes when the mcu exits stop mode. 17.6 tim during break interrupts a break interrupt stops the tim counter and inhibits input captures. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state (see figure 15-19. sim break flag control register (sbfcr) ). to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 236 freescale semiconductor break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 17.7 i/o signals port d shares one of its pins with the tim. port e shares two of its pins with the tim and port f shares four of its pins with the tim. ptd6/atd14/tclk is an external clock input to the tim prescaler. the six tim channel i/o pins are pte2/tch0, pte3/tch1, ptf0/tch2, ptf1/tch3, ptf2/tch4, and ptf3/tch5. 17.7.1 tim clock pi n (ptd6/atd14/tclk) ptd6/atd14/tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the ptd6/atd14/tclk input by writing 1s to the three prescaler select bits, ps[2:0] (see 17.8.1 tim status and control register ). the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is the least: 4 mhz or bus frequency 2. ptd6/atd14/tclk is available as a general-purpose i/o pin or adc channel when not used as the tim clock input. when the ptd6/atd14/tclk pin is the tim clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 17.7.2 tim channel i/o pi ns (ptf3/tch5?ptf0/tch2 a nd pte3/tch1?pte2/tch0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. pte2/tch0, ptf0/tch2, and ptf2/tch4 can be configured as buffered output compare or buffered pwm pins. 17.8 i/o registers these i/o registers control and monitor tim operation: tim status and control register (tsc) tim control registers (tcnth?tcntl) tim counter modulo registers (tmodh?tmodl) tim channel status and control registers (tsc0?tsc5) tim channel registers (tch0h?tch0l through tch5h?tch5l) 17.8.1 tim status and control register the tim status and control register: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock 1 bus frequency ------------------------------------- t su +
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 237 tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value. 0 = tim counter has not reached modulo value. toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupt s when the tof bit becom es set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. also, when the tstop bit is set and input capture mode is enabled, input captures are inhibited until tstop is cleared. when using tstop to stop the timer counter, see if any timer flags are set. if a timer flag is set, it must be clea red by clearing tstop, then clearing the flag, then setting tstop again. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 17-4. tim status and control register (tsc)
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 238 freescale semiconductor ps[2:0] ? prescaler select bits these read/write bits select either the ptd6/atd14/tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 17-1 shows. reset clears the ps[2:0] bits. 17.8.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note if tcnth is read during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. table 17-1. prescaler selection ps[2:0] tim clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 ptd6/atd14/tclk register name and address tcnth ? $0022 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 register name and address tcntl ? $0023 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 17-5. tim counter registers (tcnth and tcntl)
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 239 17.8.3 tim counter modulo registers the read/write tim modulo register s contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set and the tim counter resumes counting from $0000 at the next timer clock. writing to the hi gh byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note reset the tim counter before writing to the tim counter modulo registers. 17.8.4 tim channel status and control registers each of the tim channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare or pwm operation selects high, low or toggling output on output compare selects rising edge, falling edge or any e dge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation register name and address tmodh ? $0024 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address tmodl ? $0025 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 17-6. tim counter modulo registers (tmodh and tmodl)
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 240 freescale semiconductor chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when chxie = 1, clear chxf by reading tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. register name and address tsc0 ? $0026 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address tsc1 ? $0029 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 register name and address tsc2 ? $002c bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 register name and address tsc3 ? $002f bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 register name and address tsc4 ? $0032 bit 7654321bit 0 read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset:00000000 register name and address tsc5 ? $0035 bit 7654321bit 0 read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 reset:00000000 = unimplemented figure 17-7. tim channel status and control registers (tsc0?tsc5)
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 241 reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0, tim channel 2 and tim channel 4 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1 pin to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3 pin to general-purpose i/o. setting ms4b disables the channel 5 status and control register and reverts tch5 pin to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 17-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin once pwm, output compare mode or input capture mode is enabled. see table 17-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e or port f and pin ptex/tchx or pin ptfx/tchx is available as a gener al-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respective pin when pwm, input capture mode or output compare operation mode is enabled. table 17-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits.
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 242 freescale semiconductor note before enabling a tim channel register for input capture operation, make sure that the ptex/tchx pin or ptfx/tchx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note when tovx is set, a tim counter ov erflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 17-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 17-8. chxmax latency table 17-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
i/o registers mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 243 17.8.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb?msxa = 0:0) reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb?msxa 0:0) writing to the high byte of the tim channel x registers (tchxh) inhibits output compares and the chxf bit until the low byte (tchxl) is written. register name and address tch0h ? $0027 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch0l ? $0028 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch1h ? $002a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch1l ? $002b bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch2h ? $002d bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch2l ? $002e bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 17-9. tim channel registers (tch0h/l?tch5h/l)
timer interface module (tim) mc68hc908as32a data sheet, rev. 2.0 244 freescale semiconductor register name and address tch3h ? $0030 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch3l ? $0031 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch4h ? $0033 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch4l ? $0034 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address tch5h ? $0036 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tch5l ? $0037 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 17-9. tim channel registers (tch0h/l?tch5h/l) (continued)
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 245 chapter 18 development support 18.1 introduction this section describes the break module, the moni tor read-only memory (mon), and the monitor mode entry methods. 18.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features include: accessible i/o registers during break interrupts cpu generated break interrupts software generated break interrupts cop disabling during break interrupts 18.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal to the sim. the sim then caus es the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a break interrupt to occur: a cpu generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 18-2 shows the structure of the break module.
development support mc68hc908as32a data sheet, rev. 2.0 246 freescale semiconductor figure 18-1. block diagram highlighting brk and mon blocks figure 18-2. break module block diagram break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module 6-channel timer low-voltage inhibit module power-on reset module computer operating properly module m68hc08 cpu control and status registers user flash ? 32, 256 bytes user ram ? 1024 bytes user eeprom ? 512 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptf ddrf power pta ddra ddrb ptb ddrc ptc user flash vector space ? 52 bytes byte data link controller programmable interrupt timer module bdrxd bdtxd interface module arithmetic/logic unit (alu) osc1 osc2 cgmxfc rst irq v ss v dd v dda v ssa av ss /v refk v ddaref cpu registers pta7?pta0 ptb7/atd7? ptc4 ptc3 ptc2/mclk ptc1?ptc0 ptd6/atd14/tclk ptd5/atd13 pta4/atd12 ptd3/atd11? pte7/spsck pte6/mosi ptd0/atd8 ptb0/atd0 pte5/miso pte4/ss pte3/tch1 pte2/tch0 pte1/rxd pte0/txd ptf3/tch5? ptf0/tch2 v refh iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] break
break module (brk) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 247 when the internal address bus matches the value writt en in the break address registers or when software writes a 1 to the brka bit in the break status and c ontrol register, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt timing is: when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routi ne, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 18.2.1.1 flag protection during break interrupts the system integration module (sim) controls whethe r module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 15.7.3 sim break flag control register and the break interrupts subsection for each module. 18.2.1.2 tim during break interrupts a break interrupt stops the timer counter. 18.2.1.3 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. for v tst , see 19.5 5.0 volt dc electrical characteristics . 18.2.2 break module registers three registers control and monitor operation of the break module: break status and control register (bscr) break address register high (brkh) break address register low (brkl)
development support mc68hc908as32a data sheet, rev. 2.0 248 freescale semiconductor 18.2.2.1 break status and control register the break status and control register cont ains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address re gister matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = when read, break address match 0 = when read, no break address match 18.2.2.2 break address registers the break address registers contain the high and lo w bytes of the desired breakpoint address. reset clears the break address registers. address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 18-3. break status and control register (bscr) register name and address brkh ? $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 register name and address brkl ? $fe0d read: bit 7654321bit 0 write: reset:00000000 figure 18-4. break address registers (brkh and brkl)
monitor module (mon) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 249 18.2.3 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. if enabled, the break module will remain enabled in wait and stop mo des. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 18.3 monitor module (mon) this subsection describes the m onitor module (mon) and the monitor mode entry methods. the monitor allows debugging and programming of the microcontrolle r unit (mcu) through a single-wire interface with a host computer. features include: normal user-mode pin functionality one pin dedicated to serial communicati on between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer up to 28.8 kbaud communication with host computer execution of code in ram or flash flash security (1) flash programming 18.3.1 functional description figure 18-5 shows a simplified diagram of the monitor mode entry. the monitor module receives and execut es commands from a host computer. figure 18-6 shows an example circuit used to enter monito r mode and communicate with a host computer via a standard rs-232 interface. while simple monitor commands can access any memory address, the mc68hc908as32a has a flash security feature to prevent external viewing of the contents of flash. proper procedures must be followed to verify flash content. access to t he flash is denied to unauthori zed users of customer specified software (see 18.3.2 security ). in monitor mode, the mcu can execute code down loaded into ram while most mcu pins retain normal operating mode functions. all communication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configur ation and requires a pullup resistor. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
development support mc68hc908as32a data sheet, rev. 2.0 250 freescale semiconductor figure 18-5. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, ptc0 = 1, and ptc1 = 0? irq = v tst ? yes no yes no normal user mode normal monitor mode invalid user mode no host sends 8 security bytes is reset por? yes yes no are all security bytes correct? no yes enable rom disable rom execute monitor code does reset occur? conditions from table 18-1 debugging and flash programming (if flash is enabled)
monitor module (mon) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 251 figure 18-6. normal monitor mode circuit 18.3.1.1 monitor mode entry table 18-1 shows the pin conditions for entering monitor mo de. as specified in the table, monitor mode may be entered after a power-on reset (por) and w ill allow communication provided the pin and clock conditions are met. the rising edge of the internal rst signal latches the monitor mode. once monitor mode is latched, the values on ptc0, ptc1, and ptc3 pins can be changed. once out of reset, the mcu waits for the host to send eight security bytes (see 18.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecu tive logic 0s) to the host, indicating that it is ready to receive a command. 18.3.1.2 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware in stead of user code. the cop module is disabled in monitor mode as long as v tst , is applied to either the irq pin or the rst pin. table 18-2 summarizes the differences between user mode and monitor mode regarding vectors. 10 k 10 k 10 k 10 k rst irq pta0 osc1 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? v ss 0.1 f v dd c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd v dd v cc gnd 1 k ? osc2 47 pf 27 pf 4.9152 mhz 10 m ? v dda ptc3 ptc0 ptc1 v ssa v dd mc68hc08as32a 9.1 v
development support mc68hc908as32a data sheet, rev. 2.0 252 freescale semiconductor table 18-1. mode selection mode irq rst serial comm. mode selection pll cop communication speed comments pta0 ptc0 ptc1 ptc3 external clock bus frequency baud rate monitor v tst v dd or v tst 1 1 0 0 off disabled 4.9152 mhz 2.4576 mhz 9600 ptc3 determines frequency divider v tst v dd or v tst 1 1 0 1 off disabled 4.9152 mhz 1.2288 mhz 4800 user v dd or v ss v dd xxxxxenabledx x x mon08 function [pin no.] v tst [6] rst [4] com [10] mod0 [12] mod1 [14] div4 [16] osc1 [13] 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the table is an example to obtain a baud rate of 4800 or 9600. baud rate using external oscillator is bus frequency / 256. 3. external clock is a 4.9152 mhz crystal on osc1 and os c2 or a 4.9152 or 9.8304 mhz canned oscillator on osc1. 4. x = don?t care 5. mon08 pin refers to p&e microcomputer systems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 nc nc 9 10 pta0 nc 11 12 ptc0 osc1 13 14 ptc1 v dd 15 16 ptc3 table 18-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v tst ) is removed from the irq pin while in monitor mode, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. see. 19.5 5.0 volt dc electrical characteristics $fefe $feff $fefc $fefd $fefc $fefd
monitor module (mon) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 253 18.3.1.3 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. (see figure 18-7 and figure 18-8 .) the data transmit and receive rate can be anywhere up to 28.8 kbaud. transmit and receive baud rates must be identical. figure 18-7. monitor data format figure 18-8. sample monitor waveforms 18.3.1.4 break signal a start bit followed by nine lo w bits is a break signal (see figure 18-9 ). when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits before echoing the break signal. figure 18-9. break transaction 18.3.1.5 baud rate with a 4.9152-mhz crystal and the ptc3 pin high during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is low during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pll, the baud rate is determined by the mul[7:4] bits in the pll programming register (ppg). see chapter 5 clock generator module (cgm) . caution care should be taken when setting the baud rate since incorrect baud rate setting can result in communications failure. table 18-3. monitor baud rate selection monitor baud rate vco frequency multiplier (n) 123456 4.9152 mhz 4800 9600 14,400 19,200 24,000 28,800 4.194 mhz 4096 8192 12,288 16,384 20,480 24,576 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo
development support mc68hc908as32a data sheet, rev. 2.0 254 freescale semiconductor 18.3.1.6 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. figure 18-10. read transaction figure 18-11. write transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times
monitor module (mon) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 255 a brief description of each monitor mode command is given in table 18-4 through table 18-9 . table 18-4. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 18-5. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-by te order; low byte followed by data byte data returned none opcode $49 command sequence table 18-6. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo data return data from host
development support mc68hc908as32a data sheet, rev. 2.0 256 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can table 18-7. iwrite (indexed write) command description write to la st address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 18-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 18-9. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo from host data data readsp readsp echo from host sp return sp high low run run echo from host
monitor module (mon) mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 257 modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 18-12. stack pointer at monitor mode entry 18.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset wa s not a power-on reset, security remains bypassed and security code entry is not required. see figure 18-13 . figure 18-13. monitor mode entry timing condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 1 3 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 3 = wait 1 bit time before sending next byte 3 from host from mcu 1 = echo delay, approximately 2 bit times 4 4 = wait until clock is stable and monitor runs
development support mc68hc908as32a data sheet, rev. 2.0 258 freescale semiconductor upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight secu rity bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. to determine whether the security code entered is correct, check to see if bit 6 of ram address $80 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the securi ty sequence, the flash module can also be mass erased by executing an erase routine that was downl oaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank).
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 259 chapter 19 electrical specifications 19.1 introduction this section contains electrical and timing specifications. 19.2 maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 19.5 5.0 volt dc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). rating (1) 1. voltages are referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma reset and irq input voltage v tst v dd + 4.5 v
electrical specifications mc68hc908as32a data sheet, rev. 2.0 260 freescale semiconductor 19.3 functional operating range note for applications which use the lvi, freescale guarantee the functionality of the device cpu only down to the lvi trip point (v lvi ) within the constraints outlined in chapter 11 low-voltage inhibit (lvi) . 19.4 thermal characteristics rating symbol value unit operating temperature range part suffix mfn part suffix vfn part suffix cfn t a ?40 to 125 ?40 to 105 ?40 to 85 c operating voltage range v dd 5.0 0.5 v characteristic symbol value unit thermal resistance qfp (64 pins) ja 70 c/w thermal resistance plcc (52 pins) ja 50 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined from a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + (p d 2 x ja ) w/ c average junction temperature t j t a + p d x ja c
5.0 volt dc electrica l characteristics mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 261 19.5 5.0 volt dc elec trical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40c to +t a (max), unless otherwise noted. symbol min typical max unit output high voltage i load = ?2.0 ma (all ports) i load = ?5.0 ma (all ports) v oh v dd ?0.8 v dd ?1.5 ? ? ? ? v total source current i oh (tot) ??10ma output low voltage i load = 1.6 ma (all ports) i load = 10.0 ma (all ports) v ol ? ? ? ? 0.4 1.5 v total sink current i ol (tot) ??15ma input high voltage all ports, irq s, reset, osc1 v ih 0.7 x v dd ? v dd v input low voltage all ports, irq s, reset, osc1 v il v ss ? 0.3 x v dd v v dd supply current run (2) wait (3) stop (4) lvi enabled, t a = 25 c lvi disabled, t a = 25 c lvi enabled, ?40 c to +125 c lvi disabled, ?40 c to +125 c 2. run (operating) i dd measured using external square wave clock source (f bus = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. cl = 20 pf on osc2 . all ports configured as input s. osc2 capacitance linearly affects run i dd . measured with all modules enabled. typical valu es at midpoint of voltage range, 25c only. 3. wait i dd measured using external square wave clock source (f bus = 8.4 mhz). all inputs 0.2 vdc from rail. no dc loads. less than 100 pf on all outputs, cl = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with all modules enabled. typical valu es at midpoint of voltage range, 25c only. 4. stop i dd measured with osc1 = v ss . typical values at midpoint of voltage range, 25c only. i dd (5) 5. although i dd is proportional to bus frequency, a current of se veral ma is present even at very low frequencies. ? ? ? ? ? ? 25 14 100 35 ? ? 35 20 400 50 500 100 ma ma a a a a i/o ports hi-z leakage current i l ?1 ? 1 a input current i in ?1 ? 1 a capacitance ports (as input or output) c out c in ? ? ? 12 8 pf low-voltage reset inhibit tr i p recover v lv i 3.80 ? ? ? ? 4.49 v por rearm voltage (6) 6. maximum is highest vo ltage that por is guaranteed. v por 0?200mv por reset voltage (7) 7. maximum is highest vo ltage that por is possible. v porrst 0?800mv por rise time ramp rate (8) 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms high cop disable voltage (9) 9. see 8.8 cop module during break interrupts . v tst applied to rst . v tst v dd + 3.0 ? v dd + 4.5 v monitor mode entry voltage on irq (10) 10. see monitor mode description within chapter 8 computer operating properly (cop) . v tst applied to irq or rst v tst v dd + 3.0 ? v dd + 4.5 v
electrical specifications mc68hc908as32a data sheet, rev. 2.0 262 freescale semiconductor 19.6 control timing 19.7 analog-to-digital conv erter (adc) characteristics characteristic (1) 1. v dd = 5.0 vdc 0.5 v, v ss = 0 vdc, t a = ?40 c to t a(max) , unless otherwise noted. symbol min max unit bus operating frequency (4.5?5.5 v ? v dd only) f bus ?8.4mhz rst pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilhi 1.5 ? t cyc irq interrupt pulse period t ilil note 4 ? t cyc 16-bit timer (2) input capture pulse width (3) input capture period 2. the 2-bit timer prescaler is the limitin g factor in determining timer resolution. 3. refer to table 17-2. mode, edge, and level selection . t th, t tl t tltl 2 note (4) 4. the minimum period t tltl or t ilil should not be less than the number of cycles it takes to execute the capture interrupt service routine plus tbd t cyc . ? ? t cyc characteristic min max unit comments resolution 8 8 bits absolute accuracy (v refl = 0 v, v dda /v ddaref = v refh = 5 v 0.5 v) ?1 +1 lsb includes quantization conversion range (1) 1. v dd = 5.0 vdc 0.5 v, v ss = 0 vdc, v dda /v ddaref = 5.0 vdc 0.5 v, v ssa = 0 vdc, v refh = 5.0 vdc 0.5 v v refl v refh v v refl = v ssa power-up time 16 17 s conversion time period input leakage (2) (ports b and d) 2. the external system error caused by input leakage current is approximately equal to the product of r source and input current. ?1 1 a conversion time 16 17 adc clock cycles includes sampling time monotonicity inherent within total error zero input reading 00 01 hex v in = v refl full-scale reading fe ff hex v in = v refh sample time (3) 3. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. 5? adc clock cycles input capacitance ? 8 pf not tested adc internal clock 500 k 1.048 m hz tested only at 1 mhz analog input voltage v refl v refh v
5.0 vdc 0.5 v serial peripheral interface (spi) timing mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 263 19.8 5.0 vdc 0.5 v serial peripheral interface (spi) timing num (1) 1. item numbers refer to dimensions in figure 19-1 and figure 19-2 . characteristic (2) 2. all timing is shown with respect to 30% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. symbol min max unit operating frequency (3) master slave 3. f bus = the currently active bus frequency for the microcontroller. f b us ( m ) f b us ( s ) f b us /128 dc f b us /2 f b us mhz 1 cycle time master slave t cyc( m ) t cyc( s ) 2 1 128 ? t cyc 2 enable lead time t lead 15 ? ns 3 enable lag time t lag 15 ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 100 50 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 100 50 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ? ? ns 8 access time, slave (4) cpha = 0 cpha = 1 4. time to data active from high-impedance state. t a(cp0) t a(cp1) 0 0 40 20 ns 9 slave disable time (hold time to high-impedance state) t dis ?25ns 10 enable edge lead time to data valid (5) master slave 5. with 100 pf on all spi pins. t ev(m) t ev(s) ? ? 10 40 ns 11 data hold time (outputs, after enable edge) master slave t ho(m) t ho(s) 0 5 ? ? ns 12 data valid master (before capture edge) t v(m) 90 ? ns 13 data hold time (outputs) master (before capture edge) t ho(m) 100 ? ns
electrical specifications mc68hc908as32a data sheet, rev. 2.0 264 freescale semiconductor figure 19-1. spi master timing diagram note note: this first clock edge is generated inte rnally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated in ternally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 12 13 12 13
5.0 vdc 0.5 v serial peripheral interface (spi) timing mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 265 figure 19-2. spi slave timing diagram note: not defined but normally msb of character just received slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (input) mosi (output) 4 5 5 1 4 msb in bits 6?1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11
electrical specifications mc68hc908as32a data sheet, rev. 2.0 266 freescale semiconductor 19.9 clock generator modu le (cgm) characteristics 19.9.1 cgm oper ating conditions 19.9.2 cgm component information characteristic symbol min typ max unit operating voltage v dda v dd ?0.3 ? v dd +0.3 v v ssa v ss ?0.3 ? v ss +0.3 v crystal reference frequency f cgmrclk 1 4.9152 16 mhz module crystal reference frequency (1) 1. same frequency as f cgmrclk . f cgmxclk ? 4.9152 ? mhz range nominal multiplier f nom ? 4.9152 ? mhz vco center-of-range frequency f cgmvrs 4.9152 ? note (2) 2. f cgmvrs is a nominal value described and calculated as an example in chapter 5 clock generator module (cgm) for the desired vco operating frequency, f cgmvclk . mhz vco operating frequency f cgmvclk 4.9152 ? 32.0 description symbol min typ max unit crystal load capacitance (1) 1. consult crystal manufacturer?s data. c l ???? crystal fixed capacitance (1) c1 ? 2 x c l ?? crystal tuning capacitance (1) c2 ? 2 x c l ?? filter capacitor multiply factor c fact ? 0.0154 ? f/s v filter capacitor (2) 2. see 5.4.3 external filter capacitor pin (cgmxfc) . c f ? c fact x (v dda /f xclk ) ?? bypass capacitor (3) 3. c byp must provide low ac impedance from f = f cgmxclk /100 to 100 x f cgmvclk , so series resistance must be considered. c byp ?0.1? f
timer module characteristics mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 267 19.9.3 cgm acquisiti on/lock time information 19.10 timer module characteristics 19.11 memory characteristics 19.11.1 ram memory characteristics description (1) 1. v dd = 5.0 vdc 0.5 v, v ss = 0 vdc, t a = ?40c to t a(max) , unless otherwise noted. symbol min typ (2) 2. conditions for typical and maximum values are for run mode with f cgmxclk = 8 mhz, f busdes = 8 mhz, n = 4, l = 7, discharged c f = 15 nf, v dd = 5 vdc. max unit manual mode time to stable (3) 3. if c f is chosen correctly. t acq ? (8 x v dda ) / (f cgmxclk x k acq) ?s manual stable to lock time (1) t al ? (4 x v dda ) / (f cgmxclk x k trk ) ?s manual acquisition time t lock ? t acq +t al ?s tracking mode entry frequency tolerance d trk 0? 3.6 % acquisition mode entry frequency tolerance d unt 6.3 ? 7.2 % lock entry frequency tolerance d lock 0? 0.9 % lock exit frequency tolerance d unl 0.9 ? 1.8 % reference cycles per acquisition mode measurement n acq ?32 ?? reference cycles per tracking mode measurement n trk ? 128 ? ? automatic mode time to stable (1) t acq n acq /f xclk (8 x v dda ) / (f xclk x k acq) s automatic stable to lock time (1) t al n trk /f xclk (4 x v dda ) / (f xclk x k trk ) ?s automatic lock time t lock ?0.65 25ms pll jitter, deviation of average bus frequency over 2 ms (4) 4. n = vco frequency multiplied. guaranteed but not tested. refer to chapter 5 clock generator module (cgm) for guidance on the use of the pll. 0? (f crys ) x (.025%) x (n/4) % k value for automatic mode time to stable k acq ?0.2 ?? k value k trk ?0.004 ?? characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ?ns characteristic symbol min max unit ram data retention voltage v rdr 0.7 ? v
electrical specifications mc68hc908as32a data sheet, rev. 2.0 268 freescale semiconductor 19.11.2 eeprom memo ry characteristics 19.11.3 flash memory characteristics characteristic symbol min max unit eeprom programming time per byte t eepgm 10 ? ms eeprom erasing time per byte t eebyte 10 ? ms eeprom erasing time per block t eeblock 10 ? ms eeprom erasing time per bulk t eebulk 10 ? ms eeprom programming volt age discharge period t eefpv 100 ? s number of programming operations to the same eeprom byte before erase (1) 1. programming a byte more times than the specified maximum ma y affect the data integrity of that byte. the byte must be erased before it can be programmed again. ?? 8 ? eeprom write/erase cycles @ 10 ms write time ? 10,000 ? cycles eeprom data retention after 10,000 write/erase cycles ? 15 ? years eeprom programming maximum time to auto bit set ? ? 500 s eeprom erasing maximum time to auto bit set ? ? 8 ms characteristic symbol min typ max unit flash program bus clock frequency ?1??mhz flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm / erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 2. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to 0. 1?? s flash cumulative program hv period t hv (3) 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv maximum. ?? 4ms flash enduran ce (4) 4. typical endurance was evaluated for this product family. for additional information on how freescale defines typical endurance , please refer to engineering bulletin eb619. ? 10 k 100 k ? cycles flash data retention t ime (5) 5. typical data retention values are based on intrinsic capability of the technology measured at high temp erature and de-rated to 25c using the arrhenius equation. for addi tional information on how freescale defines typical data retention , please refer to engineering bulletin eb618. ? 15 100 ? years
byte data link controller (bdlc) characteristics mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 269 19.12 byte data link cont roller (bdlc) characteristics 19.12.1 bdlc tra nsmitter vpw symbol timings 19.12.2 bdlc receiver vpw symbol timings characteristic (1), (2) 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v 2. see figure 19-3 . number symbol min typ max unit passive logic 0 10 t tvp1 62 64 66 s passive logic 1 11 t tvp2 126 128 130 s active logic 0 12 t tva1 126 128 130 s active logic 1 13 t tva2 62 64 66 s start-of-frame (sof) 14 t tva3 198 200 202 s end-of-data (eod) 15 t tvp3 198 200 202 s end-of-frame (eof) 16 t tv4 278 280 282 s inter-frame separator (ifs) 17 t tv6 298 300 302 s characteristic (1), (2), (3) 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v 2. the receiver symbol timing boundaries are subject to an uncertainty of 1 t bdlc s due to sampling considerations. 3. see figure 19-3 . number symbol min typ max unit passive logic 0 10 t trvp1 34 64 96 s passive logic 1 11 t trvp2 96 128 163 s active logic 0 12 t trva1 96 128 163 s active logic 1 13 t trva2 34 64 96 s start-of-frame (sof) 14 t trva3 163 200 239 s end-of-data (eod) 15 t trvp3 163 200 239 s end-of-frame (eof) 16 t trv4 239 280 320 s break 18 t trv6 280 ? ? s
electrical specifications mc68hc908as32a data sheet, rev. 2.0 270 freescale semiconductor figure 19-3. bdlc variable pulse width modulation (vpw) symbol timing 19.12.3 bdlc transm itter dc electrical characteristics 19.12.4 bdlc receiver dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = ?40 o c to +125 o c, unless otherwise noted symbol min max unit bdtxd output low voltage (ibdtxd = 1.6 ma) v oltx ?0.4 v bdtxd output high voltage (ibdtx = ?800 a) v ohtx v dd ?0.8 ?v characteristic (1) 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = ?40 o c to +125 o c, unless otherwise noted symbol min max unit bdrxd input low voltage v ilrx v ss 0.3 x v dd v bdrxd input high voltage v ihrx 0.7 x v dd v dd v bdrxd input low current i ilbdrxi ?1 +1 a bdrxd input high current i hbdrx ?1 +1 a 13 11 10 12 16 14 sof 15 18 0 0 1 1 eod brk 0 eof
mc68hc908as32a data sheet, rev. 2.0 freescale semiconductor 271 chapter 20 ordering information and mechanical specifications 20.1 introduction this section provides ordering information fo r the mc68hc908as32a along with dimensions for: 52-pin plastic leaded chip carrier (plcc) 64-pin quad flat pack (qfp) the following figure shows the latest package drawing at the time of this publication. to make sure that you have the latest package specifications, contact your local freescale sales office 20.2 mc order numbers figure 20-1. device numbering system 20.3 package dimensions refer to the following pages fo r detailed package dimensions. table 20-1. mc order numbers mc order number operating temperature range mc68hc908as32acfn (1) 1. fn = plastic leaded chip carrier ?40c to + 85c mc68hc908as32avfn (1) ?40c to + 105c mc68hc908as32amfn (1) ?40c to + 125c MC68HC908AS32AFU (2) 2. fu = quad flat pack ?40c to + 85c mc68hc908as32acfu ?40c to + 105c mc68hc908as32avfu ?40c to + 125c m c 6 8 h c 9 0 8 a s 3 2 a x x x e family package designator temperature range pb free

ordering information and mechanical specifications mc68hc908as32a data sheet, rev. 2.0 278 freescale semiconductor

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